An Analytical Model Including Interface Traps and Temperature Effects in Negative Capacitance Double Gate Field Effect T
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ORIGINAL PAPER
An Analytical Model Including Interface Traps and Temperature Effects in Negative Capacitance Double Gate Field Effect Transistor Yibiao Dong1 · Ru Han1
· Danghui Wang1 · Ruofei Wang1 · Chenmeng Guo1
Received: 11 February 2020 / Accepted: 10 August 2020 © Springer Nature B.V. 2020
Abstract In this paper, an analytical model for negative capacitance double gate field effect transistor (NC-DG-FET) is proposed. This model includes interface traps and temperature effects, which are ignored in previous investigations. In addition, the impacts of the ferroelectric thickness tF E , the interface trap density Dit and temperature T on the device performance are comprehensively discussed. The results indicate that, the minimum subthreshold swing is about 14 mV/decade with tF E = 75 nm, Dit = 5 × 1010 cm−2 /eV , T = 300 K. As Dit increases, the flat band voltage is decreased, which results in a gain peaking at a lower gate voltage, and a steeper subthreshold slope. When the temperature is raised from 300 K to 380 K, the NC effect is gradually weakened, resulting in a decrease in gain, and a smoothing of the subthreshold slope. We have verified our model by comparing it with experimental data and numerical simulation. Keywords Analytical model · Negative capacitance · Ferroelectric thickness · Interface traps density · Temperature
1 Introduction Traditional MOSFETs have a physical limitation on the subthreshold swing (SS), which is about 60 mV/dec at room temperature. To solve this problem, the negative capacitance field effect transistor (NCFET) has been proposed. Furthermore, NCFET is compatible with the traditional process technology. Together with the recent breakthrough in material development, NCFET is considered as an excellent solution to the power consumption problem. However, if we want to specifically apply this device to chip manufacturing, we still need to do a lot of research. Among them, one aspect involved is the establishment of analytical model. An accurate, computational model that fits the physical mechanism of the device is essential for us to carry out larger-scale circuit design. From this perspective, the establishment of analytical model is particularly necessary. And a number of groups have recently proposed different analytical models of NCFET [1–6]. For example, Lee et al. proposed a semi-analytical model, integrating both numerical and analytical approach to take the advantages Ru Han
[email protected] 1
School of Computer Science and Engineering, Northwestern Polytechnical University, Xi’an, 710129, China
from both [1]. Peng et al. comprehensively studied the influence of ferroelectric material properties on the electrical characteristics of the NC Ge pFETs utilizing the analytical model [5]. Jiang et al. developed a fully-analytical current-voltage model to describe the electrical behavior of back-gated 2D junctionless NC-FETs [6]. However, the interface traps and temperature effects are rarely considered in these analytical models at the same time. The interface trap state
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