Charge Storage Mechanism in Nano-Crystalline Si Based Single-Electron Memories
- PDF / 624,236 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 75 Downloads / 196 Views
Charge Storage Mechanism in Nano-Crystalline Si Based Single-Electron Memories Bruce J. Hinds, Takayuki Yamanaka, and Shunri Oda Research Center for Quantum Effect Electronics Tokyo Institute of Technology 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552 Japan ABSTRACT A memory device sensitive to a single electron stored in a nanocrystalline Si dot has been synthesized allowing for the study of charge retention lifetime. A 50 nm by 20 nm transistor channel is synthesized by E-beam lithography followed by reactive ion etching of thin (20nm) Silicon-on-Insulator (SOI) channel. This small area of the narrow channel allows for the isolation of a single nano-crystalline Si dot and elimination of channel percolation paths around the screening charge. Remote Plasma Enhanced CVD is used to form 6±2nm diameter nc-Si dots in the gas phase from a pulsed SiH4 source. Electrons stored in a dot results in an observed discrete threshold shift of 90 mV. Analysis of lifetime as a function of applied potential and temperature show the dot to be an acceptor site with nearly Poisson lifetime distributions. An observed 1/T2 dependence of lifetime is consistent with a direct tunneling process, thus interface states are not the dominant mechanism for electron storage in this device structure. Median lifetimes are modeled by a direct tunneling process, which is influenced by gate bias and dot size. INTRODUCTION Devices sensitive to a single electron have the possibility to drastically improve memory and logic device performance by high device density and low power. With current scaling trends in metal oxide semiconductor field effect transistors (MOSFET) production there is the inevitable need to understand and optimize devices that operate with only a statistically small number of electrons whose transport is mesoscopic. Si based nanoscale devices are strong contenders due to existing Si process infrastructure as well as the nearly perfect interface between SiO2 dielectric and Si. The latter advantage is paramount to success, since single electronic devices are obviously sensitive to local and background charged defects. Several groups have demonstrated single electron memory effects in Si systems. Examples include charge stored in nanocrystalline Si dots (nc-Si) above large area FET channel[1], charge stored in single poly-Si dot over narrow SOI channel [2-4], and memory devices based on charge through complex percolation paths of several nm thick SOI [5]. Generally there is a significant trade off between short write/erase time and long memory retention time, which is determined mainly by the tunnel oxide thickness. The write time is reported to be many orders of magnitude faster than retention time [1], which is not expected if both write and erase process are due to direct tunneling. One possible explanation for the long retention time is that stored electrons are trapped in interface states on the Si nanocrystals. The effects of interface states on single electron memory has been shown to be important after H passivation of interface sta
Data Loading...
