CMOS Ultra-High-Speed Time-Interleaved ADCs

CMOS technologies have been able to fabricate ultra-high-speed time-interleaved (TI) ADCs that achieve a sampling rate over 10 GS/s. The TI architecture relaxes the speed requirement for each A/D channel. It also introduces inter-channel mismatches that c

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CMOS Ultra-High-Speed Time-Interleaved ADCs Jieh-Tsorng Wu, Chun-Cheng Huang, and Chung-Yi Wang

Abstract CMOS technologies have been able to fabricate ultra-high-speed time-interleaved (TI) ADCs that achieve a sampling rate over 10 GS/s. The TI architecture relaxes the speed requirement for each A/D channel. It also introduces inter-channel mismatches that cause conversion errors. These errors can be reduced by calibration. An 8-channel 6-bit 16-GS/s TI ADC is presented to illustrate several circuit design and calibration techniques. Each A/D channel is a 6-bit flash ADC. The low-power comparators in the flash ADC are latches with offset calibration. A delaylocked loop generates the 8-phase sampling clocks for the TI ADC. Timing-skew calibration is used to ensure uniform sampling intervals. Both the offset calibration and the timing-skew calibration run continuously in the background. This TI ADC was fabricated using a 65 nm CMOS technology. At 16 GS/s sampling rate, this chip consumes 435 mW from a 1.5 V supply. It achieves a signal-to-distortion-plus-noise ratio (SNDR) of 30.8 dB. The ADC active area is 0:93  1:58 mm2

5.1

Introduction

CMOS technologies have been able to fabricate ultra-high-speed analog-to-digital converters (ADCs) that provide sampling rates beyond 10 GS/s [1–6]. These are time-interleaved (TI) ADCs with multiple analog-to-digital (A/D) channels, such as 80 current-mode pipelined ADCs [1], 160 SAR ADCs [2, 4], 8 pipelined dual-path ADCs [3], and 8 flash ADCs [5, 6]. Advanced CMOS technologies provide two crucial circuits for ultra-high-speed TI ADCs: (1) input samplers using MOST switches and (2) multi-phase clock generators with a fine timing resolution.

J.-T. Wu (*) • C.-C. Huang • C.-Y. Wang Department of Electronics Engineering, National Chiao-Tung University, 1001 Ta-Hsueh Road, Hsin-Chu 300, Taiwan e-mail: [email protected] A.H.M. van Roermund et al. (eds.), Nyquist AD Converters, Sensor Interfaces, and Robustness: Advances in Analog Circuit Design, 2012, DOI 10.1007/978-1-4614-4587-6_5, # Springer Science+Business Media New York 2013

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An ADC periodically samples an analog input and digitizes the magnitude of each sampled analog signal into a digital code. Both the input sampler and the magnitude digitizer must meet the speed and resolution requirements. The TI architecture relaxes the speed requirement for the magnitude digitizer. However, the requirements for the input sampler get harsher. The TI architecture also introduces inter-channel mismatches that cause analog-to-digital (A/D) conversion errors. The remainder of this paper is organized as follows. Section 5.2 discusses the design issues for ultra-high-speed TI ADCs, which include input sampler, inter-channel mismatches and calibrations. Section 5.3 describes an 8-channel 6-bit 16-GS/s TI ADC. It is presented to illustrate several circuit design and calibration techniques. This ADC contains an offset calibration scheme and a timing-skew calibration scheme that can run continuously in the backgroun