Contact Resistance Improvement for Advanced Logic by Integration of Epi, Implant and Anneal Innovations
- PDF / 1,617,723 Bytes
- 18 Pages / 432 x 648 pts Page_size
- 61 Downloads / 341 Views
MRS Advances © 2019 Materials Research Society DOI: 10.1557/adv.2019.416
Contact Resistance Improvement for Advanced Logic by Integration of Epi, Implant and Anneal Innovations Fareen Adeni Khaja Applied Materials, 974 E Arques Ave., Sunnyvale, CA 94041, USA
Phone : +1-408-563-7178 E-mail : [email protected]
ABSTRACT As advanced CMOS scaling with FinFETs continues beyond the 10/7nm nodes, contact resistance (Rc) remains a dominant component affecting device performance. The FinFET Source/Drain (S/D) contact area has become smaller with fin pitch scaling, resulting in drastically increased Rc. To achieve higher drive currents and fully realize the performance gain from FinFET architectural changes, it is critical to continue to reduce contact resistivity (ρc) < 1.0x10-9 Ω.cm2 for both NMOS and PMOS. In this paper, we review the recent trends for ρc reduction for advanced CMOS devices and discuss approaches that have demonstrated reduction in ρc, such as in-situ heavily doped epitaxial films for S/D, advanced ion implantation and laser anneals. The implant techniques include pre-amorphization implants (PAI), dopant boosting implants, cryogenic (-100ºC) implants for damage engineering and plasma doping (PLAD) for conformal doping of high aspect ratio (HAR) contacts. With such high levels of doping from epi and implants, advanced laser anneals are key for epitaxial regrowth and formation of metastable alloys for dopant supersaturation or segregation in top layers. Millisecond laser anneal (MSA) improves dopant activation and nanosecond laser anneal (NLA) permits superactivation, and both have become key enablers for ρ c reduction. This paper also reviews two alternative contact approaches: dual silicide scheme and wraparound contact (WAC), as potential pathways to further reduce Rc for advanced CMOS nodes.
Downloaded from https://www.cambridge.org/core. Access paid by the UCSB Libraries, on 18 Nov 2019 at 12:54:18, subject to the Cambridge Core terms of use, available at https://www.cambridge.org/core/terms. https://doi.org/10.1557/adv.2019.416
INTRODUCTION As complementary metal–oxide–semiconductor (CMOS) Logic technology scaling with fin field-effect transistors (FinFETs) continues beyond the 7nm node, the industry is evaluating integration of several options to squeeze advances out of silicon, including new materials: Ge for high-mobility channel for PMOS, 2D semiconductors (with transition metal dichalcogenides (TMDC), such as MoS2, MoSe2, ZrSe2) for high electron mobility for NMOS; and compact device architectures: gate all around (GAA) transistors with nanosheets or nanoslabs, and forksheets pushing the n and p transistors closer together [1, 2]. Advanced architectural concepts include vertical CMOS formed with complementary transistor pairs stacked vertically. A radical reworking is envisaged for the system on chip (SoC) by sequential monolithic 3D integration with throughsilicon vias (TSV) to separate and optimize for the different needs of power, logic and memory circuits, with buried power rai
Data Loading...
