Control of Polysilicon Emitter Bipolar Transistor Characteristics by Rapid Thermal or Furnace Anneal of the Polysilicon/
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CONTROL OF POLYSILICON EMITTER BIPOLAR TRANSISTOR CHARACTERISTICS BY RAPID THERMAL OR FURNACE ANNEAL OF THE POLYSILICON/SILICON INTERFACE S. BHATTACHARYA*, M. LOBO*, L. JUNG*, S. BANERJEE*, R. REUSS**, S. BATRA***, K. PARK****, AND G. HU**** * Microelectronics Research Center, The University of Texas, Austin, TX 78712 ** Motorola Inc., Scottsdale, AZ 85258 Micron Semiconductor, Boise, ID 83706 **** Cypress Semiconductor, San Jose, CA 94134 ABSTRACT In this paper we report on the ability of rapid thermal annealing (1050C, 45s) and furnace annealing (900C, 30min) to partially break up the interfacial oxide in bipolar transistors with different oxide thicknesses at the polysilicon/silicon interface. We have obtained the different oxide thicknesses either by performing different ex situ cleans (RCA clean or RCA clean + HF dip) before Low Pressure Chemical Vapor Deposition (LPCVD) of polysilicon, or by using a cluster tool for polysilicon deposition with the ability to perform an in situ clean and then allowing the growth of different oxide thicknesses at the interface prior to polysilicon deposition. For the in situ cleaned devices, it is observed that after the interface anneal, the current gain increases with increasing oxide thicknesses, but with little penalty in terms of higher emitter resistance, Re. This indicates that by controllably increasing the interfacial oxide thickness and by subsequent annealing to partiallybreak up the interfacial oxide, higher current gains can be obtained with little sacrifice in terms of higher Re. INTRODUCTION Advanced self-aligned bipolar transistors use polysilicon-contacted emitters to achieve high gain and reduced parasitic capacitances which are critical for high speed applications. In using polysilicon emitters, it is crucial to control the properties of the interface between polysilicon and the underlying single crystal silicon in order not to have excessively high emitter resistance, Re, while still achieving an acceptable enhancement of current gain, 13.The polysilicon/silicon interface has a thin layer of oxide which is beneficial as a tunneling barrier to minority carrier hole transport, thereby reducing the base current and increasing P3.However, it also acts as a resistive barrier to majority carrier electron transport in NPN transistors, thereby increasing Re. The furnace anneal or a rapid thermal anneal that is used to outdiffuse dopants and form a shallow, abrupt emitter-base junction also serves to partially "break up" the interfacial oxide, and reduce Re, while still retaining the minority carrier blocking properties of the polysilicon/silicon interface. The impact of annealing on the interfacial oxide break up and the polysilicon emitter bipolar transistor characteristics has been reported before [1]. We examine the effects of varying the oxide thickness on the interfacial oxide break up and the resulting controllability of the final device parameters. Our experiments were performed on self-aligned polysilicon emitter transistors. The 2000A thick polysilicon film
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