Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors
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Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors Nihar Ranjan Mohapatra, Souvik Mahapatra and V. Ramgopal Rao Department of Electrical Engineering Indian Institute of Technology, Bombay, 400 076, India. ABSTRACT This paper analyzes in detail the substrate enhanced gate current injection mechanism and the resulting hot-carrier degradation in n-channel MOS transistors and compares the results with conventional channel hot carrier injection mechanism. The degradation mechanism is studied for different values of substrate voltage over a wide range of channel length and oxide thickness. Stress and charge pumping measurements are carried out to study the degradation under identical bias (gate, drain, substrate) and gate current condition. The influence of device dimensions on the gate injection efficiency and hot carrier degradation is also studied. Results show that the degradation under negative substrate voltage operation is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanism responsible for such trends is discussed. It is also found that, under identical gate current (programming time in flash memory cells), the degradation is less for higher negative substrate bias, which is helpful in realizing fast and reliable flash memories. INTRODUCTION Channel Hot Electron (CHE) programming is one of the most widely used methods to program flash devices. The major disadvantages of using CHE injection for programming flash cells are: the large voltages required (VDS > 5V, VGS > 10V) and the higher drain current, which poses serious limitation for low power digital systems. These problems become more of an obstacle as the power supply is reduced and the technology is scaled to smaller dimensions and higher densities. Recently, a new electron injection mechanism is activated upon application of a negative substrate voltage (VB) [1-4]. This mechanism is called as CHannel Initiated Secondary ELectron Injection (CHISEL), which provides promise for fast and low power non-volatile memories. Although in the recent past, a significant effort has been devoted to understand the physics behind this mechanism, not much work has been done at studying its reliability issues. In this paper we have studied in detail the reliability issues of n-channel MOS transistors operating under different reverse substrate bias over a wide range of channel length and oxide thickness. We have measured the gate current by using a highly sensitive floating gate technique. Hot carrier stress and charge pumping measurements have been carried out to study the degradation under identical bias (gate, drain, substrate) and identical injection condition. Post stress interface state generation and the resulting drain current degradation has been studied as functions of gate and drain bias on devices having different channel lengths and oxide thickness. We found that the injection mechanism and thereby damage with negative VB is more sensitive to the transverse electric field. Wi
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