Epitaxial lanthanide oxide thin films on Si for high- k gate dielectric application: Growth optimization and defect pass
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Andrea Fissel and Hans Jörg Osten Institute of Electronic Materials and Devices, Leibniz University Hannover, D-30167 Hannover, Germany (Received 31 August 2016; accepted 4 January 2017)
Epitaxial layers of insulating binary lanthanide oxides have been considered as potential alternative to conventional SiO2 for gate dielectric application in future Si-based MOSFET devices, which was investigated in more detail for epitaxial Gd2O3 and Nd2O3 as model systems. Additionally, the ability to integrate epitaxial dielectric barrier layers into Si structures can usher also in a variety of novel applications involving oxide/silicon/oxide heterostructures in diverse nanoelectronic and quantum-effect devices. Although epitaxial layers of such ionic oxides with excellent structural quality can be grown using molecular beam epitaxy, they often exhibit poor electrical properties such as high leakage current density, flat band instability, poor reliability etc. owing to the presence of electrically active charge defects, generated either during the oxide layer growth or typical subsequent CMOS process steps. Based on the origin and individual character of these defects, we review various aspects of defect prevention and passivation which lead to a significant improvement in the dielectric properties of the heterostructures.
I. INTRODUCTION
The physical dimension of metal oxide field effect transistors (MOSFETs) which are essential components of semiconductor integrated circuits (ICs) have been subjected to continuous downscaling since the birth of ICs to improve the device performance and reduce the production cost per bit. This shrinking of the semiconductor device dimension follows an empirical trend popularly known as Moore’s law, which describes that the number of transistors per IC, or in other words processing capacity and speed doubles, every two years.1 Moore’s prediction was found true for a long while thanks to the rapid advancement of semiconductor device processing technologies such as lithography, selective etching processes etc. On the other hand from the materials aspect, the key material property that enabled the existence of Si-MOSFET devices is the excellent insulating characteristic of SiO2 thin layers which is used as the gate dielectric to isolate the transistor gate from the Si channel. This is possible due to the large band gap of SiO2 (Eg ;9 eV), and the low density of interface traps with Si. For example, in advanced integrated devices SiO2 gate dielectrics with charge densities of 1010 cm2, midgap interface state densities of 1010 cm2, and dielectric strength of Contributing Editor: Don W. Shaw a) Address all correspondence to this author. e-mail: [email protected] This paper has been selected as an Invited Feature Paper. DOI: 10.1557/jmr.2017.22
15 kV/cm have been produced.2,3 Further, high quality layer of SiO2 can be grown by simple thermal oxidation that remains amorphous at typical CMOS process condition which is less prone to any structural defects. However, it was evident that continuing
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