Ferroelectric Thin Films Grown on Base-Metal Foils for Embedded Passives
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Ferroelectric Thin Films Grown on Base-Metal Foils for Embedded Passives Beihai Ma, Do-Kyun Kwon, Manoj Narayanan, and U. (Balu) Balachandran Argonne National Laboratory, Argonne, IL, 60439 ABSTRACT Development of electronic devices with higher performance and smaller size requires the passive components to be embedded within a printed wire board (PWB). The “film-on-foil” approach is the most viable method to fabricate suitable passive components. We have deposited high-permittivity thin films of ferroelectric Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) on base metal foils by chemical solution deposition. These capacitors could be embedded into PWBs. However, formation of a parasitic low-permittivity interfacial layer of nickel oxide during thermal processing of the PLZT films considerably reduces the capacitance density. Two approaches were taken to overcome the problem. In the first, a conductive buffer layer of lanthanum nickel oxide (LNO) was inserted between the PLZT film and the nickel foil to hinder the formation of deleterious interfacial oxide. In the second, high temperature processing was done under low oxygen partial pressure such that no interfacial oxide was formed. By these approaches, we have grown high-quality ferroelectric PLZT films on nickel and copper foils. With samples of PLZT grown on LNO-buffered Ni, we measured a dielectric constant of 1300 (at 25°C) and 1800 (at 150°C), leakage current density of 6.6 x 10-9 A/cm2 (at 25°C) and 1.4 x 10-8 A/cm2 (at 150°C), and breakdown field strength >1.2 MV/cm. With samples of PLZT on Cu, we obtained encouraging initial results of dielectric constant >450 and dielectric loss tan(δ) ≈0.04. INTRODUCTION Embedding capacitors into a printed wire board (PWB) would free up surface space, increase device reliability, minimize electromagnetic interference and inductance loss, and reduce manufacturing cost. Miniaturization can be realized through replacing the surface-mounted components and interconnects, which would lead to a reduction in the wire board size. Reliability is expected to increase due to the reduced number of solder joints and shortened interconnects [1]. This also helps to reduce wire inductance on the board and increase the maximum frequency of operation. Manufacturing cost is likely to be decreased because of the ability to place packaging with pre-embedded capacitive layers without the need for pick-andplace assembly operations, which very often constitute an appreciable fraction of the manufacturing cost and decrease assembly line throughput. Photolithographic methods in combination with etching and metallization steps can be used to synthesize the needed capacitive elements and interconnections rapidly and in large quantity [2]. While this technology has primarily received attention for decoupling capacitors in microelectronic applications, it can also be extended to higher voltage applications. One area where it holds particular promise is for applications that require high capacitance density and high volumetric efficiency, such as power
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