Integration of fullerenes and carbon nanotubes with aggressively scaled CMOS gate stacks
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Integration of fullerenes and carbon nanotubes with aggressively scaled CMOS gate stacks Udayan Ganguly1, Chungho Lee2 and Edwin C. Kan2 Department of Materials Science and Engineering, 2School of Electrical and Computer Engineering, Cornell University
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ABSTRACT Here we report the first study towards the integration of fullerenes and carbon nanotubes (CNT) in the gate stack of CMOS technology, which is a promising hybrid approach of top-down and bottom-up fabrication process. Prospective processes for C60 and CNT deposition over an aggressively scaled 2 nm gate oxide in the MOS capacitor structure have been monitored. CV measurements show minimal silicon contamination and interface states. Step charging at a specific voltage that corresponds to a fixed number density of C60 is used to establish the structural integrity and size-mono-dispersion of C60. The CV method can be further used to probe the charge injection into C60 and its anions to establish fundamental understanding of their molecular orbital (MO) structure. INTRODUCTION Integration of carbon nanotubes and fullerenes in silicon electronics is a new promising direction for device miniaturization towards the nanoscale. Conventional complimentary metal oxide semiconductor (CMOS) technology with the deep sub-50 nm drawn gate length [1] is pushing the limit of lithographic dimensions that can be mass produced. At this size scale and smaller, nature manufactures structures by self assembly with great precision and reliability. However, combination with top-down design patterns will collectively determine the functional density, because self-assembled homogeneous structures do not contain asymmetry to represent designerdefined information. Hence, a hybrid of bottom-up and top-down approach for device fabrication can provide critical links to engineering in the nanoscale. Carbon nanotubes (CNT) and fullerenes have also stimulated great scientific interest. Carbon has rich chemistry and it selfassembles into these structures of low dimensions. The C60 molecules can be used to replace nanocrystals in non-volatile memory devices. The mono-disperse nature and small size of C60 in comparison with self-assembled semiconductor and metal nanocrystals [2-4], which have nonnegligible size variation, will lead to large and accurate step charging into molecular orbitals (MO) and hence can potentially provide reliable multiple-level storage in a single device. On the other hand, CNT can be used as floating gates in CĪ½MOS for nanometer scale sensor applications [5] and scaling studies beyond lithographic dimensions. However, there are imminent challenges towards the goal of integration. MOS processing may involve high energy plasma and high temperature processes that can adversely affect the single or few shells of atoms that constitute the C60 and CNT. Conversely, the new materials in the CMOS gate stack can potentially contaminate and degrade the MOS structure during processing. Hence a mutually compatible process development is necessary for any integration plan.
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