Junctions for Deep Sub-100 NM MOS: How Far will Ion Implantation Take Us?
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JUNCTIONS FOR DEEP SUB-100 NM MOS: HOW FAR WILL ION IMPLANTATION TAKE US? H.-J. Gossmann, C. S. Rafferty, and P. Keys* Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974 *
University of Florida, Gainesville, FL 32611
ABSTRACT We analyze the requirements that the International Technology Roadmap for Semiconductors (ITRS) implicitly imposes on the two-dimensional source/drain (SD) dopant profile and translate the results into implant parameters (energy, dose, peak concentration). We do this by determining the voltage drop that the SD current develops across the three main (exclusive of the channel) resistive components in the current path: the spreading resistance in the extension region; the metal-semiconductor contact; and the resistance in the link-up region where the SDregion meets the channel. The largest resistance occurs in the link-up region, followed by the resistance of the contact; the extension contribution is the smallest. The extension resistance requirement can be satisfied by ion-implantation for all generations of the ITRS. The link-up region requires very abrupt lateral profiles, not demonstrated so far by ion-implantation. It is found that such resistance cannot be reduced without impacting the intrinsic device behavior. The contact eventually necessitates dopant concentrations in excess of solid solubility and for NMOS in excess of the fundamental limit of dopant activation. INTRODUCTION Producing the junctions for transistors with sub-100 nm gate-lengths is a significant challenge. For many reasons, such as uniformity, reproducibility, and cleanliness, ion implantation is presently the method of choice for the formation of the source/drain (SD) junctions and the channel. On the other hand, ion implantation creates defects, giving rise to a host of undesirable effects, such as dopant clustering and transient enhanced diffusion. A clear-cut path to a solution that satisfies all constraints is by no means obvious.
Rc ρext s Lext Rlnk
Rch
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Figure 1. Cross-section of MOSFET (schematic); the three series-resistance components, contact resistance, R c , extension resistance, ρ ext s L ext , and link-up- or tip- resistance, R lnk , are shown.
In this paper we analyze the requirements that the 1999 edition of the International Technology Roadmap for Semiconductors[1] (ITRS) implicitly imposes on the two-dimensional SD
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dopant profile and translate the results into implant parameters (energy, dose, peak concentration). There are three main (exclusive of the channel) resistive components in the current path: (1) the spreading resistance in the extension region, R ext ; the metal-semiconductor contact, R c ; and the resistance in the link-up- or tip- region where the SD-region meets the channel, R lnk . For each component we determine the dopant profile required to keep the voltage drop across that component on both sides of the transistor at 5% of the supply voltage, V DD . As specified in the Roadmap, the SD current is taken as 0.75
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