Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack
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ORIGINAL PAPER
Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET Dharmender1 · Kaushal Nigam1 Received: 3 September 2020 / Accepted: 3 November 2020 © Springer Nature B.V. 2020
Abstract In this paper, we investigate the effect of low K dielectric pocket on DC and analog/RF performance in dual material stack gate oxide double gate tunnel field effect transistor. For this, we have considered an optimized dielectric pocket at the interface of the source-channel tunneling junction to reduce the barrier width. A stack gate oxide (SiO2 +Hf O2 ) with workfunction engineering is applied to improve the capacitive coupling, decrease the ambipolar, leakage currents and increase the ON-current (ION ). In addition, the entire gate has been divided into three segments, named as tunnelling gate (M1 ) with workfunction (φ1 ), Control gate (M2 ) with workfunction (φ2 ) and auxiliary gate (M3 ) with workfunction (φ3 ). All the possible combinations of these workfunctions were considered to maintain dual work functionality. Further, technology computer-aided design (TCAD) simulations for these possible combinations were carried out and compared with single material stack gate oxide dual gate source dielectric pocket TFET (φ1 = φ2 = φ3 ). Simulation results shows that the workfunction combination (φ1 = φ3 < φ2 ) outperforms the other three structures. Further, the performance of this device is compared with dual material control gate source dielectric pocket TFET (DMCG-SDP-TFET) with SiO2 gate oxide. The dielectric pocket at the tunneling junction and workfunction engineering on the stack gate oxide shows significant enhancement in ON state current (1.47×10−4 A/μm), ION /IOF F (3.14×1012 ), point subthreshold slope (15.7mV /decade), transconductance (1.02×10−3 S), cut-off frequency (1.93×1011 H z) and significant changes in other analog/RF performance parameters, making this device suitable for high frequency and low power applications. Keywords Dual material · Stack gate oxide · Dielectric pocket · Tunnel field effect transistor · Workfunction
1 Introduction To improve the switching speed, packing density, analog/RF performance and reduce the power dissipation, the dimensions of conventional MOSFETs are continuously scaling down to a few nanometers. This results in some critical issues like leakage current, high power dissipation, short channel effects (SCEs) and a sub-threshold slope restriction of 60 mV/decade for conventional MOSFETs at room temperature [1–6]. To overcome the above issues, an alternative device tunnel field-effect transistor (TFET) seems Kaushal Nigam
[email protected] 1
Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, 201304, India
more suitable due to low OFF current, steeper subthreshold slope below 60 mV/decade, possibility of supply voltage scaling, better immunity to short channel effects and temperature variations [7, 8]. These capabilit
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