Reverse Diode Leakage in Spike-Annealed Ultra-Shallowjunctions
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REVERSE DIODE LEAKAGE IN SPIKE-ANNEALED ULTRA-SHALLOW JUNCTIONS Hans-Joachim L. Gossmann Agere Systems, Murray Hill, NJ Tao Feng University of Florida, Gainesville, FL Aditya Agarwal, Peter Frisella and Leonard M. Rubin Axcelis Technologies, Beverly, MA
ABSTRACT We have investigated diode leakage in junctions produced by ion-implantation of B with energies of 0.5 - 2 keV and doses of 2 × 1014 — 2 × 1015 cm−2 into n-type wells of ∼1 × 1018 cm−3 , after rapid-thermal anneals (RTA) in lamp-based and hot-wall furnaces. Junctions are as shallow as 30 nm and were directly probed to avoid complications arising from metalization. The leakage current, I lkg , was found to be independent of the implant dose at any reverse voltage (-1 and -5 V). This implies that the electrically active defects are sufficiently far removed and on the surface-side of the junction. In both systems, a spike anneal (no intentional dwell time at peak-temperature) resulted in higher I lkg than a soak anneal (dwell time of several seconds at peak-temperature). However, for the same spike annealing recipe, the hot-wall RTA produces tighter distributions than the lamp-based RTA. The width of the distribution is a measure of the temperature uniformity across the wafer. Best leakage currents are of the order 1 × 10−6 A/cm2 , in good agreement with device simulations The shallowest junctions exhibit I lkg ∼ 5 × 10−4 A/cm2 , still well below the specification of even the low power transistor of a 100 nm technology. INTRODUCTION The 1999 International Technology Roadmap for Semiconductors (ITRS-99)1 specifies for a 100 nm Si technology junction depths of less than 30 nm at the channel and less than 70 nm at the source/drain contact. For many reasons, such as uniformity, reproducibility, and cleanliness, ion implantation is presently the method of choice for the formation of these junctions. On the other hand, ion implantation creates defects, giving rise to a host of undesirable effects, such as dopant clustering and transient enhanced diffusion.2 Hence, during processing, every attempt is made to minimize diffusion, with the consequence that the dopants are not driven very far beyond the region of ion-implantation-induced damage. The Roadmap also demands for the 100 nm node an extension sheet resistance as low as 200 Ω/ . While is has recently been argued3 4 that a sheet resistance of ∼1kΩ/ suffices, this still requires very high dopant concentrations. The demand for small diffusive distances translates into a low thermal budget, whereas high electrically active dopant concentrations imply a high annealing temperature, where the solid solubility is large. Therefore, "spike"-anneals, i.e. rapid thermal anneals (RTA) with nominally zero dwell time at the peak temperature, have become the method of choice for activating the junctions.5 6 J8.4.1
The temperature uniformity across the wafer is an issue with spike-anneals and together with the low thermal budget and the very high dopant concentrations may lead to excessive junction leakage current, I lkg . In
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