Study of CoSix Spike Leakage for 0.1-um CMOS
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Study of CoSix Spike Leakage for 0.1-um CMOS Ken-ichi Goto Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-0197 Japan ABSTRACT We have clarified a new leakage mechanism in Co salicide process for the ultra-shallow junctions of 0.1-um CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents generate from many localized points that are randomly distributed in the junction area, and not from the junction edge. We successfully verified our localized leakage model using Monte Carlo simulation. We identified abnormal CoSix spiking growth under the Co silicide film, as being the origin of the localized leakage current. These CoSix spikes grow rapidly only during annealing between 400°C and 450°C when Co2Si phase is formed. These spikes never grow during annealing at over 500°C, and decrease with high temperature annealing over 500°C. A minimum leakage current can be achieved by optimized annealing at between 800°C and 850°C for 30 sec. This is because a trade-off between reducing the CoSix spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900°C. INTRODUCTION In deep sub-micron complementary metal oxide semiconductor (CMOS) devices, reduction of parasitic resistance is a key issue for high-speed operations [1]. A self-aligned silicide (salicide) process is an attractive approach for reducing both the sheet resistance of the gate and source/drain regions and the contact resistance to them. Recently, Ti salicide process has been widely used in mass production of LSI logic devices. However, with shortening of gate length, it becomes more difficult to achieve low sheet resistance in the Ti salicide process by the following two reasons. One is a difficulty in a crystal phase transformation from high resistivity C49 phase to low resistivity C54 phase, and the other is agglomeration of the Ti silicide film in gate structures shorter than 0.1-um long [2], [3]. As an alternative material, Co salicide process has been intensively used. Recent studies have reported that by using a TiN-capping process, Co salicide successfully realizes the low gate sheet resistance of 5 ohm/sq down to 0.075-um gate length [1, 2, 4]. However, the Co salicide process causes a severe junction leakage, which becomes increasingly serious when the junction depth was scaled down to 0.1-um and below. C9.1.1
This paper reviewed the junction leakage mechanism of Co salicide process for 0.1-um CMOS technology. We verified this leakage model using Monte Carlo simulation and identified CoSix spikes which grow abnormally under the Co silicide film as the origin of the leakage current. We developed a low-leakage and low-resistance Co salicide process by using a high temperature annealing and a TiN-capping process for sub-0.1-um CMOS devices. EXPERIMENTS The n+/p-diodes were fabricated with a conventional LOCOS process and implanted with boron ions under the same conditions as in n-MOSFET channel fabrication.
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