The piezoelectronic transistor: A nanoactuator-based post-CMOS digital switch with high speed and low power
- PDF / 1,192,118 Bytes
- 8 Pages / 585 x 783 pts Page_size
- 97 Downloads / 154 Views
Introduction The development of the ubiquitous information technology (IT) industry has been driven by Moore’s law on transistor scaling, the exponential increase in complementary metal oxide semiconductor (CMOS) transistor density on a chip with time. Also key to performance improvement is the associated increase in clock speed, enabled by a systematic reduction in voltage with time (Dennard or classical scaling1). The voltage reduction concomitant with the speed increase is vital, as otherwise increased speed would result in increases in power and hence in unacceptable heat production. After 2003, the voltage could no longer be lowered below about 1 V because a fundamental physical limit of the CMOS transistor had been reached2 that then stalled further increases in speed. The fundamental limit on voltage arises from the need to turn the device off by applying an electrostatic potential to the channel, creating a statisticalmechanical barrier that single carriers (electrons/holes) find hard to cross.2 The barrier height cannot be larger than the electronic charge e times line voltage VDD, while the temperature T sets a scale kBT for the carrier energy, where kB is the Boltzmann constant. Since eVDD/kBT must not fall below a certain value for effective switch-off, there is a floor under the line voltage
value at room temperature. Engineering and materials science innovation applied to CMOS cannot overcome its fundamental physical limitation, and hence the only route to restore scaling is the development of a conceptually novel low voltage/low power and high frequency device.3 If developed and implemented successfully, the new device could reinvigorate the IT industry. Approaches toward developing an alternative computer switch concept have been reviewed by Theis and Solomon.3,4 They included “energy filtering,” as exemplified by the tunnel field-effect transistor (FET),5 “internal potential step-up,” as illustrated by the ferroelectric-gate FET6 and quantum capacitive devices,7 and “internal transduction.” Among the latter are the spin-FET8 and nano-electromechanical switch.9 However, none of the present embodiments of the mentioned concepts has been demonstrated to perform at a level that would make it competitive with the FET as device scales are further reduced. In response to this challenge, a new device concept, the piezoelectronic transistor (PET) has been put forward (see Figure 1a). Simulations of the PET design, described later, show that it can indeed meet the challenge of operability at low voltages and higher speeds than conventional CMOS. The
D.M. Newns, IBM Research Division, T.J. Watson Research Center; [email protected] B.G. Elmegreen, IBM Research Division, T.J. Watson Research Center; [email protected] X.-H. Liu, IBM Research Division, T.J. Watson Research Center; [email protected] G.J. Martyna, IBM Research Division, T.J. Watson Research Center; [email protected] DOI: 10.1557/mrs.2012.267
© 2012 Materials Research Society
MRS BULLETIN • VOLUME 37 • NOVEMBER 2012 • www.mrs.org/bulletin
1071
THE
Data Loading...
