Thermal Stability of Ir/TaN Electrode/Barrier on Thin Gate Oxide for MFMOS one Transistor Memory Application
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INTRODUCTION FeRAM with Metal-Ferroelectric-Insulator-Silicon (MFIS) and MetalFerroelectric-Silicon (MFS) structures have been found to have disadvantages for nonvolatile memory applications because of the poor retention property. One of the reasons is diffusion happens between the ferroelectric, insulating layer and silicon substrate, and subsequently, poor interface properties between these layers are noted[l]. Furthermore, both structures are rather difficult to fabricate. On the other hand, FeRAM with the Metal-Ferroelectric -Metal-Oxide-Silicon (MFMOS) structure has been considered to have better interface properties due to the improved barrier property of the metal electrode. It is also easier to fabricate[2]. The MFMOS FET enables the use of conventional ferroelectric capacitors and MOSFETs. Fujimori et al has proposed a MFMOS transistor with Pt/IrO2/Poly-Si/Gate Si0 2 as the electrode in which the gate oxide is 13nm and polysilicon is 150 nm[3]. We have attempted to use a more simplified yet still reliable structure to fabricate MFMOS memory in which the bottom electrode and thin conductive barrier layer directly contact the thin gate Si0 2 . The structure we
67 Mat. Res. Soc. Symp. Proc. Vol. 596 ©2000 Materials Research Society
used is ft/TaN/gate Si0 2 in which the thickness of gate Si0 2 is around 30 A. It is well known that Ir has good barrier properties towards oxygen diffusion[4,5]. TaN is a stable barrier layer on the Si substrate[6,7]. Furthermore, the If/TaN electrode/barrier structure was also very stable on silicon and silicon oxide substrates[8]. In this paper, the If/TaN/Gate Si0 2 capacitor was formed and the thermal stability and reliability of the structure was studied by annealing the structure in oxygen and nitrogen ambients then characterized by C-V and I-V studies. EXPERIMENTAL The Ir/TaN/Gate Si0 2 capacitors were formed on 150mm diameter p-type (100) Si substrates. Openings were made in 1000A thermal oxide by photopatterning and HF wet etching, followed by gate oxidation using a 02/N 20 recipe at 850 'C that results in a 30A nitrided oxide. Three different TaN films prepared with different nitrogen/ argon flows ratios at 60 sccm/40 sccm (No.1), 50 sccm/50 sccm (No.2), and 40 sccm/80 sccm (No.3) in the reactive sputter chamber were investigated. For the TaN with nitrogen/argon ratio at 50 sccm/50 sccm, two different thickness at 220 A and 440 were deposited. The reactive sputter was performed at 300'C using a Ta target of 99.95% purity at a DC power of 3 kW. The film thicknesses were characterized with XRD reflectivity. Immediately after TaN deposition, the Ir film was e-beam evaporated at 225°C to a thickness of about 1500A. The final If/TaN/Gate Si0 2 capacitor was defined by dry etching. Anneals were performed in an oxygen ambient at temperatures ranging from 500 to 650 'C for duration from 5 to 90 min. Rapid thermal annealing was also performed in nitrogen ambient at 1000°C for 10s. A forming gas annealing was also performed to improve the interface regions. Capacitors with areas
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