The Nucleation and Growth of GaAs on Si
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THE NUCLEATION AND GROWTH OF GaAs ON Si J. S.
HARRIS,
Jr., S. M. KOCH AND S. J. ROSNER*
Stanford University, Department of Electrical Engineering, McCullough 208, Stanford, CA 94305 *also with Hewlett-Packard Circuit Technology Group, Deer Creek Road, Palo Alto, CA 94306 ABSTRACT
Substantial progress has been realized in both understanding the nucleation and growth of GaAs/Si and demonstration of device application of this technology. In this paper, we review the recent progress in the role of the Si surface, initial nucleation, the GaAs/Si interface, GaAs thick layer growth and defect generation and control in the GaAs layer. This last area is the remaining area where substantial progress is still required. Several new approaches for defect control are discussed. INTRODUCTION
The growth of GaAs on Si has been recognized as a highly desirable technology goal for a number of years. The earliest work focused on solar cells because they were very large area devices where the substrate cost, maximum substrate size, ruggedness and weight (for space applications) were major obstacles for conventional GaAs homoepitaxial approaches. Si substrates provided an attractive solution to all of the above problems. In addition, the alloy composititon of AIGaAs can be adjusted to provide an optimum bandgap and absorption match to Si for high efficiency multiple bandgap solar cells. There were major DoE and SERI supported solar cell efforts at Jet Propulsion Labs [1-2], MIT Lincoln Labs [3-5], Renssalaer Polytechnic Institute [6], Rockwell International [7-9] and Southern Methodist University [10-11]. Many of these efforts attempted the growth of GaAs directly on both single and polycrystal Si, but with very little success. This was not a surprising result because of the expected heteroepitaxial problems created by a 4% lattice mismatch, large thermal expansion mismatch and polar/non-polar interface with antiphase disorder, cross doping and phase segregation. These initial efforts then evolved into a variety of approaches utilizing refractory metals, Ge or Si-Ge graded layers with subsequent growth of GaAs. These structures still faced the polar/non-polar interface problems. While reasonably efficient GaAs on Ge single crystal cells were realized [13-14], the results with various interfacial layers on Si were disappointingly inferior. The best result was 14% efficiency achieved by Tsaur, et al. using a Ge interlayer [12]. About 1982, the potential advantages of optical interconnects, optoelectronic integrated circuits (OEIC) and monolithic integration of ultra-high speed GaAs with high density Si VLSI pushed a re-examination of the earlier difficulties of direct GaAs/Si heteroepitaxy. There were three key results which have greatly changed the outcome from the prior failures. First was the ability to achieve a clean (relatively 0 and C free) Si surface. Kroemer, et. al. [15] and Ishizaka, et al. [16] demonstrated two different techniques suitable for cleaning Si at the relatively low temperatures compatible with GaAs MBE system
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