Sub 50nm Strained n-FETs Formed on Silicon-Germanium-on-Insulator Substrates and the Integration of Silicon Source/Drain
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Sub 50nm Strained n-FETs Formed on Silicon-Germanium-on-Insulator Substrates and the Integration of Silicon Source/Drain Stressors Grace Huiqi Wang1, Eng-Huat Toh1, Keat-Mun Hoe2, S. Tripathy3, Guo-Qiang Lo2, Ganesh Samudra1, and Yee-Chia Yeo1 1 Electrical and Computer Engineering, National University of Singapore, Silicon Nano Device Lab Engineering drive 3, Singapore, 459441, Singapore 2 Institutue of Microelectronics, Singapore, 117685, Singapore 3 Institute of Materials Research & Engineering, Singapore, 117602, Singapore ABSTRACT Silicon (Si) source and drain (S/D) regions have been successfully integrated in thin-body silicon-germanium-on-insulator (SGOI) n-FETs. The selectively grown Si S/D induces uniaxial tensile strain in the SiGe channel. Lattice mismatch between the silicon S/D region and the SiGe channel was exploited to induce lateral tensile strain and vertical compressive strain in the channel, leading to enhancement in electron mobility. Devices with gate length LG down to 50 nm were fabricated. For transistors fabricated on Si0.60Ge0.40-on-insulator substrates, devices with Si S/D give 40% higher saturation drain current IDsat than devices with Si0.60Ge0.40 S/D. When the Ge content is reduced in Si0.75Ge0.25-on-insulator substrates, the lattice mismatch between the S/D and the channel for devices with Si S/D is reduced, and a lower IDsat enhancement of 27% is reported over devices with Si0.75Ge0.25 S/D and channel regions. Analyses of contributions from the tensile strain to mobility enhancement and performance improvement are discussed.
INTRODUCTION As MOSFETs are scaled into the sub-45 nm technology regime, conventional scaling for improving device performance becomes inadequate to realize high performance levels projected in the International Technology Roadmap for Semiconductors. Novel materials and integration schemes are therefore being used to provide enhancement of device characteristics. Group-IV high-mobility semiconductors such as Ge [1] and SiGe [2] have received considerable attention as potential materials for further extension of transistor performance. Exploitation of strainedGe and SiGe channels would lead to further reduction in carrier effective mass and mobility enhancement, paving the way for high mobility transistors with superior on-current and speed performance. Existing work on SiGe channel shows marginal enhancement in NMOS [3], possibly due to the compressive stress in the thin SiGe channel structures. By adopting silicongermanium-on-insulator (SGOI) substrates fabricated by a novel Ge condensation technique [4], the lateral compressive strain normally present in SGOI substrates can be reduced, enabling the realization of nFETs with good performance on such substrates.
In this work, we report the experimental demonstration of uniaxial tensile strained thinbody silicon-germanium-on-insulator (SGOI) n-FETs with silicon (Si) source and drain (S/D) regions. Due to the mismatch in lattice constant between the channel and the S/D material, the selectively grown
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