Chemical beam deposition of high- k gate dielectrics on III-V semiconductors: TiO 2 on In 0.53 Ga 0.47 As
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1155-C13-02
Chemical beam deposition of high-k gate dielectrics on III-V semiconductors: TiO2 on In0.53Ga0.47As Roman Engel-Herbert1, Yoontae Hwang1, James M. LeBeau1, Yan Zheng2, and Susanne Stemmer1 1 Materials Department, University of California, Santa Barbara, CA 93106-5050, U.S.A. 2 Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106-5050, U.S.A. ABSTRACT We report on the growth of high-permittivity (k) TiO2 thin films on In0.53Ga0.47As channels by chemical beam deposition with titanium isopropoxide as the source. The films grew in a reaction-limited regime with smooth surfaces. High-resolution transmission electron microscopy showed an atomically abrupt interface with the In0.53Ga0.47As channel that indicated that this interface is thermally stable. Measurements of the leakage currents using metal-oxidesemiconductor capacitors with Pt top electrodes revealed asymmetric characteristics with respect to the bias polarity, suggesting an unfavorable band alignment for CMOS applications. X-ray photoelectron spectroscopy was used to determine the TiO2/In0.53Ga0.47As band offsets. A valence band offset of 2.5 ± 0.1 eV was measured. INTRODUCTION The scaling of conventional, Si-based complementary metal oxide semiconductor (CMOS) field-effect-transistors (FETs) is approaching its fundamental limits. High-mobility semiconductor channel materials, such as III-V compound semiconductors or Ge, have the potential to enable further scaling of FETs, thus allowing for higher speed and lower operating voltages. The realization of III-V based MOSFETs requires the development of suitable gate dielectrics. These dielectrics should be thermally stable in contact with the semiconductor and should allow for a low density of interface states and low leakage currents, which require sufficient band offsets with the semiconductor. For scaling, a high dielectric constant is also necessary. One of the main challenges in III-V CMOS is that oxygen exposure of the semiconductor surface must be prevented because native III-V oxides can cause Fermi level pinning even at sub-monolayer coverage [1]. Several binary oxides, such as Al2O3 [2,3], ZrO2 [4] and HfO2 [5,6], have been investigated for use as high-k dielectrics on InGaAs channels, mainly by atomic layer deposition (ALD). This deposition technique combines several advantages, such as low temperature, large area uniformity and precise thickness control. Ideally, however, a growth environment is desired where the dielectric is deposited on a well-defined, clean III-V surface without any oxidation of the semiconductor during deposition. This would allow for distinguishing between the intrinsic properties of different high-k/III-V combinations and those arising from interface degradation during gate stack deposition, such as unintentional oxidation. One way to achieve this is to use chemical beam deposition in ultrahigh vacuum on III-V surfaces that have never been exposed to air, which can be obtained by As-capping after growth
and de-cappin
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