CMP-induced Peeling in Multi-level Ultra Low-k / Cu Interconnects
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0914-F12-07
CMP-induced Peeling in Multi-level Ultra Low-k / Cu Interconnects Patrick Leduc1, Thierry Farjot1, Mylène Savoye1, Anne-Cécile Demas1, Sylvain Maitrejean1, and Gerard Passemard2 1 CEA-LETI, 17 avenue des Martyrs, Grenoble, F-38054, France 2 STMicroelectronics, 850 rue Jean Monnet, Crolles, F38926, France
ABSTRACT This work shows that the addition of dielectric levels in an interconnect stack increases significantly the CMP-induced peeling. The fracture energies, measured by 4-point bending technique, are less sensitive to the level number increase, even if they are slightly degraded. This leads to the conclusion that delamination during polishing depends highly on the stack elastic properties and there is no simple correlation between stack adhesion and peeling during CMP. In this work, mechanical damages generated during CMP in the dielectric stack before peeling were also investigated. It was shown that, if no peeling appears, CMP have no effect on stack reliability. This indicates that negligible “fatigue” effect takes place during CMP.
INTRODUCTION In on-chip copper interconnects, inter-metal dielectric materials are known to have low elastic modulus, low fracture toughness and poor adhesion to cap and liner layers [1-2]. Damages as cohesive fracture and interface debonding can occur during integration processes as chemical mechanical polishing (CMP) and packaging. By measuring the wafer peeling during CMP, it was previously shown [3-5] that delamination depends on the adhesion of the weakest interface of a stack, and on the elastic modulus of the dielectric films. In this paper, the same experimental methodology is applied to characterize the effect of increasing number of ultra low-k (ULK) layers on peeling during CMP. In multi-level interconnects, peeling could be mainly influenced by two factors. With the addition of copper/ULK levels, the evolution of stack stiffness and residual stresses will induce modified deformations and strains during CMP, which may have an effect on delamination [6]. Moreover, irreversible dielectric damages generated during each inter-level CMP could impact stack mechanical reliability. These damages could be sub-critical crack growth, considered as “fatigue”, or slurry diffusion in ULK. These aspects will be investigated in this work through polishing experiments and 4-point bending measurements.
EXPERIMENTAL DETAILS Experiments were performed using wafers with one to three levels of dielectric stack composed of a 300nm ultra low-k (ULK) film between two hydrogenated amorphous silicon carbide interlayers (a-SiC:H), as shown in figure 1-a. ULK material is a spin-on glass
organosilicate film with 36% porosity. Its reduced modulus is measured by nanoindentation at 2GPa. The stack adhesion was tuned by applying a dioxygen plasma treatment on a-SiC:H surface prior ULK deposition. The dielectric stacks were metallized with 10nm MOCVD TiN barrier, 60nm CVD copper seed layer and 650nm ECD copper, and then annealed at 400°C during 30mn in furnace. These stacks are named M1
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