Development of 3D-Packaging Process Technology for Stacked Memory Chips
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0970-Y03-06
Development of 3D-Packaging Process Technology for Stacked Memory Chips Toshiro Mitsuhashi1, Yoshimi Egawa1, Osamu Kato1, Yoshihiro Saeki1, Hidekazu Kikuchi1, Shiro Uchiyama2, Kayoko Shibata2, Junji Yamada2, Masakazu Ishino2, Hiroaki Ikeda2, Nobuaki Takahashi3, Yoichiro Kurita3, Masahiro Komuro3, Satoshi Matsui3, and Masaya Kawano3 1 SIP Engineering Department, Oki Electric Industry, 550-1 Higashiasakawa, Hachioji, Tokyo, 192-0912, Japan 2 Elpida Memory, Kanagawa, Japan 3 NEC Electronics, Kanagawa, Japan
ABSTRACT A 3D packaging technology for 4 Gbit DRAM has been developed. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Interconnect between stacked chips will be done by through-silicon-via for the requirement of 3Gbps operation. Key process technologies for chip stacking are through-silicon-via formation, wafer back side process and micro-bump bonding. These chip-stacking processes have been developing using TEG, which can evaluate electrical characteristics. INTRODUCTION LSI system innovation has been done in parallel with advanced packaging technologies. Strong demand on higher performance, higher operation speed and smaller occupancy area is now requiring stacked chip packaging (3D-LSI) with Through-Silicon-Via (TSV) technology that is breakthrough of interconnect bottleneck among chips [1][2]. Since 3D-LSI with TSVs can handle huge amount of data transfer among LSI layers, we are able to make LSI system faster and smarter. This chip stacking technology is adoptable especially for DRAM that has to be small, high-density and high-speed at the same time. Elpida Memory, NEC Electronics and Oki Electric Industry collaborate to develop staked memory chip technology supported by the New Energy and Industry Technology Development Organization (NEDO) [3]. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Joint development of chip-stacked, high-speed, high density DRAM technology is targeting to realize 4Gb density DRAM by stacking eight 512Mb DRAM cores. Interconnect between stacked chips by TSVs can separate high-speed I/O functions onto separated Interface-Chip for 3Gbps operation. At the same time, "Interposer" will be developed to re-allocate via/bump location. These 3 elements (DRAM core, Interface-chip, Interposer) will be mounted into one package (Fig. 1).
Conventional Single Layer DRAM
Chip Stack DRAM With Through Silicon Via(TSV) Internal Bus
TSV
DRAM Core DRAM Core
Peripherals
DRAM Core 4Gbit Density DRAM Core
DRAM Core DRAM Core DRAM Core DRAM DRAMCore Core
Interposer
8 Layers Peripherals 3Gbps/pin
Figure 1. Concept of chip-stacked DRAM TSV and development target.
with
OUTLINE OF CHIP STACKING PROCESS Core process for chip stacking The feature of our process is having chosen the Via First in the TSV formation. The TSV formation method is classified into two kinds of Via First and Via Last. Furthermore, Via Last is classified into Front side and Back side (Table 1). From a viewpoint of process flexibility, Vi
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