Drain-engineered vertically stacked junctionless FET exhibiting complementary operation
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Drain‑engineered vertically stacked junctionless FET exhibiting complementary operation M. Ehteshamuddin1 · Sajad A. Loan1 · M. Rafat2 Received: 10 May 2020 / Accepted: 30 September 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract In this work, a multifunctional drain-engineered (DE) vertically stacked (VS) junctionless (JL) FET exhibiting device reconfigurability and its application as an inverter are proposed and simulated. The proposed DE VS JL FET consists of stacked n+ and p+ device layers having SiO2 isolation vertically, with n-drain ( Dn ) and p-drain ( Dp ) silicide regions connected together. Highly doped device layers allow for the formation of a thin-dopant segregation layer on the drain side. To mimic the realistic channel/drain junctions, silicides with realistic Schottky-barrier heights are chosen ( Dn : ErSix ≈ 0.28 eV and Dp : PtSi ≈ 0.24 eV). Both device layers contribute individually to the n-FET and p-FET complementary operation when biased adequately. Moreover, the transient analysis shows that the device in the inverter mode performs reasonably well even when the VDD is scaled up to 0.5 V. Furthermore, a 3-transistor-based 2-input XOR gate standard cell has also been realized using the proposed device. Keywords Junctionless-FET · Multifunctional · CMOS alternative
1 Introduction The evolution of transistors in the semiconductor industry has mainly been driven by the aggressive scaling of the device physical dimensions. This has enabled us to suppress the short-channel-effects (SCEs) and improve the device electrostatic integrity, which results in better switching speed, packing density and functionality [1, 2]. However, the ongoing CMOS scaling is hampered by the total power dissipation in an integrated circuit (IC) due to the increase in leakage current and, simultaneously, the difficulty in the supply voltage, VDD , scaling [3, 4]. To counter this, development of advanced transistor architectures including nanowire (NW) FETs [5–7], nanotube (NT) FETs [8, 9], tri-gate and FinFET transistors [10–13] alongside alternate current transport band-to-band tunneling * Sajad A. Loan [email protected]
M. Ehteshamuddin [email protected]; [email protected]
1
Department of Electronics and Communication Engineering/ Applied Sciences, Jamia Millia Islamia, New Delhi, India
Department of Applied Sciences, Faculty of Engineering, Jamia Millia Islamia, New Delhi 110025, India
2
(BTBT) devices (both lateral [14] and line architectures [15]) has been in progress. However, as we reach into the sub-10 nm regime, another problem arises is the need of ultra-sharp doping profiles at junctions, which turns out to be indispensable for proper transistor action and therefore, requires ultra-fast annealing techniques [16]. This, in turn, raises the thermal budget significantly. To overcome this, a relatively simpler concept of junctionless (JL) FET has been proposed, wherein a device layer is uniformly doped ( n+ or p+ ) and the workfunction difference between the semic
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