Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon
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https://doi.org/10.1007/s11664-020-08332-2 Ó 2020 The Minerals, Metals & Materials Society
INTERNATIONAL ELECTRON DEVICES AND MATERIALS SYMPOSIUM 2019
Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon Gate-All-Around Nanowire n-MOSFETs WEN-LI SUNG1,2 and YIMING LI
1,2,3,4,5
1.—Parallel and Scientific Computing Laboratory, National Chiao Tung University, Hsinchu, Taiwan. 2.—Institute of Communications Engineering, National Chiao Tung University, Hsinchu, Taiwan. 3.—Department of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan. 4.—Center for mmWave Smart Radar System and Technologies, National Chiao Tung University, Hsinchu 300, Taiwan. 5.—e-mail: [email protected]
In this study, we present a statistically accurate model to predict the threshold-voltage variability (rVth) efficiently for three-dimensional (3D) vertically stacked silicon (Si) gate-all-around (GAA) nanowire (NW) n-MOSFETs with multi-channels. The statistical results indicate that the rVth decreases exponentially by increasing metal grain number (MGN), which is unitless. Additionally, the magnitude of rVth was calculated for various MGNs, which joins the normality test with Anderson–Darling test. Therefore, the model with MGN can be implemented by nonlinear regression with a regression coefficient of approximately one. From this model and the perspective of process, more 3D vertically stacked channels can reduce the value and sensitivity of rVth. This study provides useful information from statistics to explain the experiment results for 3D vertically stacked Si GAA NW nMOSFETs with multi-channels. Key words: Gate-all-around, nanowire, metal grain number, threshold voltage, variability, sensitivity
INTRODUCTION Three-dimensional (3D) vertically silicon (Si) gate-all-around (GAA) nanowire (NW) MOSFETs with high-j/metal-gate (HKMG) technology are promising devices to replace the fin-type-field effect transistor (FinFET) in emerging technology because of the device’s density and excellent performance.1–4 However, the deposition process of a metal gate on high-j dielectrics in a relatively smaller gate area forms different crystal orientations and grain sizes of nanosized metal grains during the high-temperature process.5,6 This produces distributions of threshold-voltage (Vth) within a wafer, wafer–wafer,
(Received December 6, 2019; accepted July 13, 2020)
and lot–lot due to different work-functions (WK) at different locations of the metal-gate/high-j interface. Moreover, the work-function fluctuation (WKF)-induced rVth was estimated to be a dominant fluctuation source by 3D device simulations for one-channel Si GAA NW MOSFETs.7,8 However, 3D device simulations will suffer from huge computational time to estimate nanosized-metal-grain-induced threshold-voltage variability (rVth) for 3D vertically stacked Si GAA NW n-MOSFETs (for example, 100 channels). This is because devices with more channels must calculate more grid points by 3D devi
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