Electrical modeling and simulation of nanoscale MOS devices with a high-permittivity dielectric gate stack
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Electrical modeling and simulation of nanoscale MOS devices with a high-permittivity dielectric gate stack J.L. Autran1, D. Munteanu, M. Houssa2, M. Bescond, X. Garros3, C. Leroux3 Laboratoire Matériaux et Microélectronique de Provence – L2MP (UMR CNRS 6137), Bâtiment IRPHE, BP 146, 49 rue Joliot Curie, F-13384 Marseille Cedex 13, France 1 also with Institut Universitaire de France (IUF) – Corresponding author ([email protected]) 2 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium 3 CEA-LETI, 17 avenue des Martyrs, BP 85X, F-30854 Grenoble Cedex 1 ABSTRACT The electrical behavior of decananometer MOS transistors with high-κ dielectric gate stack has been investigated using 2D numerical simulation. Two important electrostatic limitations of high-κ materials have been analyzed and discussed in this work: i) the gate-fringing field effects which compromise short-channel performance when simultaneously increasing the dielectric constant and its physical thickness and ii) the presence of discrete fixed charges in the gate stack, suspected to be at the origin of the stretch-out of C-V characteristics, that induces 2D potential fluctuations in the structure. In both cases, the resulting degradation of transistor operation and performance is evaluated with a two-dimensional quantum simulation code. INTRODUCTION High-permittivity (high-κ) dielectrics are currently widely investigated for the replacement of SiO2 as gate insulator in decananometer metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs). Indeed, at this scale of integration, the scaling down of MOS devices is confronted to the limitation of ultra-thin gate oxides which approach their physical and electrical limits, especially from the point-of-view of gate leakage current limitation. In other words, the exponential increase of the gate leakage current, due to direct tunneling effect, clearly becomes untenable for circuit operation when reducing the gate oxide thickness below a physical thickness of ~1-2nm [1]. To prevent direct gate tunneling, the replacement of SiO2 by alternative materials with higher permittivity and greater physical thickness is definitively envisaged, especially for low power applications. However, the introduction of these high-κ dielectrics poses several majors problems that impact device physics and process integration. On the electrical point-of-view, much effort has recently been devoted to the understanding of fundamental limitations of high-κ materials, including the essential question of carrier mobility degradation, the unresolved problem of the Fermi level pinning or the process-control of electrically-active defects and related instabilities in these materials [1]. In this work, numerical simulations are used to explore and predict the effect of some electrostatic limitations of high-κ materials on the electrical response of MOS capacitors and nanoscale MOS transistors. Double-Gate (DG) MOSFET architecture has been considered in this study because of its very promising performances with respect to the International Tec
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