Modified Core-Shell Double Gate Junctionless MOSFET with High ON-State and Low Leakage Currents
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ORIGINAL PAPER
Modified Core-Shell Double Gate Junctionless MOSFET with High ON-State and Low Leakage Currents Ajay 1 Received: 8 November 2019 / Accepted: 4 December 2019 # Springer Nature B.V. 2019
Abstract In this proposed article, an investigation has been studied for low leakage current and high on-state current with heavily doping in source and drain region of Double Gate Junctionless Metal Oxide Semiconductor Field-Effect Transistor (DG JL MOSFET). Conventional DG JL MOSFET is facing problem in fabrication because of high contact resistance at source and drain region. This contact resistance can be reduced by considering heavily doping in source and drain region but this leads to high leakage current for Conv. JL MOSFET. However, low doping, narrow channel thickness and high work function gate materials are used Conv. DG JL MOSFET and Core-Shell DG JL MOSFET are providing low leakage current but on-state current is also reduced. The proposed modified Core-Shell DG JL MOSFET with heavily doping in source and drain to reduce the contact resistance is displaying low leakage current with high amount of on-state current. RF performance such as Trans-conductance, capacitance, Cut-off frequency, maximum operating frequency and intrinsic power gain (S21), have also been investigated of modified CoreShell DG JL MOSFET. Keywords Core-Shell . Cut-off frequency . Double gate . Junctionless MOSFET . Radio frequency . Trans-conductance
1 Introduction Several efforts have been done by semiconductor research society to achieve cost-effective, miniaturized, high-speed and low-power consuming devices. The mentioned features can only be possible by device scaling and approach to new device architectures [1]. Device scaling is a wonderful tool to enhance the device performance, but continuously scaling leads to short channel effects (SCE), namely drain induced barrier lowering, threshold voltage roll-off, hot carrier, velocity saturation, impact ionization and sub-threshold swing which seriously affect the device behavior. Numerous efforts such as halo doping, super-steep retrograde channel doping, shallow source drain extensions, high-K dielectric replacing the gate oxide and metal gates instead of poly gates have been done in past to improve the short channel effects (SCEs) [1–3]. Further, many multi-gate architectures such as Double
* Ajay [email protected] 1
Advanced Nanoelectronic Device & Circuit Characterization Research Group, Department of Electronics System Engineering, Indian Institute of Science, Bangalore 560012, India
Gate MOSFET, Surrounding-Gate/Gate All Around (SG/ GAA) MOSFET, nanowires, nanotubes and FinFETs have been proposed as some alternative solutions to reduce the SCE and improve the gate controllability [4–8]. However, the above-stated device architectures have p-n junction between the source/drain and the channel which poses a great difficulty in the fabrication at the nanoscale spectrum. To overcome this technological problem, some new innovative MOSFET designs have been proposed in past. Jun
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