Microbump Impact on Reliability and Performance in Through-Silicon Via Stacks
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Microbump Impact on Reliability and Performance in Through-Silicon Via Stacks 1
Aditya P. Karmarkar1 and Xiaopeng Xu2 Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh 500032, India. 2 Synopsys, Inc., Mountain View, CA 94043, U.S.A.
ABSTRACT The impact of microbump geometry, layout and underfill material properties on the device performance as well as the structural reliability is examined. Numerical simulations reveal that the magnitude of n-type carrier mobility change correlates with the increase in the underfill CTE and modulus as well as microbump pitch and height, but the decrease in the microbump radius. The crack driving force dependence on material property and geometry differs from that of mobility change. While the driving force is crack location dependent, the greater crack driving force corresponds to larger underfill CTE and bump radius, but smaller underfill modulus and microbump pitch. INTRODUCTION Three dimensional (3D) integration using through-silicon via (TSV) technology provides high integration densities, heterogeneous integration and enhanced system performance [1] – [3]. The TSV induced stress effects on device performance and reliability have been examined previously [4], [5]. In case of 3D integrated chips that employ the TSVs, microbumps are used to connect vertically stacked silicon chips. The 3D chip stack with microbumps forms an intricate geometry with materials that have widely varying thermo-mechanical properties [6], [7]. The microbumping and stacking operations introduce mechanical stresses that depend on the process cycle, microbump and underfill materials, geometry, and layout. These stresses alter the carrier mobility in the active regions of the silicon chip and consequently affect the device performance. They may also act as a damage driving force for interface debonding and/or cracking and result in mechanical and electrical failures in the 3D chip stack. It is essential to examine the performance and reliability impact of microbump induced stresses in order to create robust and reliable 3D integration designs. The mechanical stress evolution during microbumping process and 3D integration assembly is examined in this paper. Here, an advanced FEM-based 3D process simulator that accounts for various stress sources is employed to generate realistic 3D structures and analyze performance and reliability impact of the microbumps [8]. The effects of microbump geometry, layout, and materials on the mechanical stress, and hence the device performance and structural reliability, are examined. The results are used to develop stress management strategies to minimize reliability and performance impact in the 3D chip stack with microbumps. NUMERIC SIMULATIONS 3D structures with stacked silicon dies are examined to assess the impact of microbump geometry and underfill material property variation on the carrier mobility in active silicon and on the structural reliability. Figure 1 (A) shows two silicon dies connected with a microbump array. The simulation boundary conditions are
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