A Two-Step Spacer Etch for High-Aspect-Ratio Gate Stack Process
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A TWO-STEP SPACER ETCH FOR HIGH-ASPECT-RATIO GATE STACK PROCESS Chien Yu, Rich Wise*, Anthony Domenicucci IBM Microelectronics, Semiconductor Research & Development Center, East Fishkill, NY 12533 *DRAM Development Alliance IBM/Infineon ABSTRACT A highly selective nitride etch was developed for gate stack spacer process in advanced memory programs. Based on methyl fluoride chemistry with better than 8:1 selectivity of nitride:oxide, this process exhibits minimal erosion to the underlying RTO thermal oxide for consistent diffusion ion-implant control. As the groundrule changed to 0.175um and below, a two-step etch scheme was employed to maintain the profile control in high-aspect-ratio structures. The stability and repeatability of the process is demonstrated in the SPC chart of the post etch FTA site measurement.
INTRODUCTION As the semiconductor devices evolve rapidly into the deep sub-micron regime, the use of silicon nitride poly gate spacer has become ever more entrenched. Besides being a highly effective isolating material (compared to oxide), the nitride spacer also enhances the gate fringing field effect due to its high dielectric constant for improved device performance [1], particularly for the densely packed array area. The combined use of thick nitride cap layer and nitride spacer also provides the best protection for gate silicide during borderless contact etch from shorting to the subsequent diffusion contact fill in DRAM technologies. The nitride spacer is typically made by an anisotropic dry etch of a conformally deposited silicon nitride layer around the gate stack after the poly re-oxidation. It is essential to select etch process with high selectivity to oxide and with minimal lateral etch. With high selectivity to oxide the nitride etch can be stopped on the screen (sidewall) oxide with minimal oxide erosion. This would eliminate the possibility of silicon damage in the diffusion area, and provide a robust and reproducible screen oxide for diffusion ion implant. With minimal lateral etch a sidewall spacer conformal around the gate stack with near as-deposited thickness next to silicide can be obtained for best isolation. The unrelenting trend of increasing array density and decreasing effective gate-length results in a corresponding increase of aspect ratio of the gate stack over time. Toward the end of 0.35 um DRAM technology generation, we have developed a highly selective nitride spacer etch based on methyl fluoride chemistry to replace an older HBr/Cl2 based process. In the subsequent generations we found that the increase of the gate trough aspect ratio resulted in a gradual increase of foot. This can be a potential issue if the spacer process is followed by diffusion ionimplant. The extent of the foot became severe enough in 0.175um generation that a two-step
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etch scheme was further developed to resolve the profile control issue, while preserving the desirable high selectivity etch as overetch step to soft-land on the screen oxide. EXPERIMENTAL Process development work was done in
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