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B4.4.1

Barrier Integrity Effect on Leakage Mechanism and Dielectric Reliability of Copper/OSG Interconnects Yunlong Li1,2, Zsolt T kei1, Tushar Mandrekar3, Bencherki Mebarki4, Guido Groeseneken1,2, Karen Maex1,2 1 IMEC, Kapeldreef 75, 3001 Leuven, Belgium 2 Department of Electrical Engineering, Katholieke Universiteit Leuven, 3001 Leuven, Belgium 3 Copper PVD Integration Systems and Modules, Applied Materials, CA 95054, USA 4 Maydan Technology Center Group, Applied Materials, Santa Clara, CA, USA ABSTRACT In this paper, we investigate the effect of copper diffusion barrier integrity on the leakage behavior and dielectric reliability of copper/micro porous organo-silica-glass (OSG) interconnects. Significant differences in the field dependence of TDDB median-time-to-failure are observed when comparing sub-critical and sealing barriers. Also for the temperature acceleration of TDDB, a significant difference is found which is reflected in the thermal activation energies. With fast voltage ramp measurements, I-V curves of samples with subcritical and sealing barriers are compared before and after constant current stresses. Above 1.4 MV/cm, the dominant leakage mechanism is found to be Frenkel-Poole emission regardless of barrier treatments and stress times. Below 1.4 MV/cm, however, the I-V characteristic is modulated by the barrier integrity, which can be attributed to copper diffusion into the intermetal dielectric. INTRODUCTION With the introduction of low-k dielectrics into on-chip interconnects to reduce the RC delay and power consumption, a dramatic reliability degradation has been found compared to the traditional oxide interconnects [1, 2]. Copper damascene structures consist of a stack of copper, a copper diffusion barrier layer and a low-k dielectric, among which the barrier integrity is believed to have a significant influence on the interconnect reliability [3, 4, 5, 6]. For copper/low-k interconnects under use conditions, one of the most important reliability concerns is increased leakage current between neighboring metal lines. The possible leakage paths include the one through the bulk dielectric and the one along the integration interfaces, for example the CMP interface. Concerning the latter one, several reports have been published, demonstrating the influence of the cap interface on leakage and reliability [7, 8]. To achieve a lower interconnect resistivity, ultra thin barrier layers are preferred. However, a very thin barrier layer may have a poor integrity. In order to test the sensitivity of our methodology and to be able to assess copper in the OSG dielectric, we intentionally selected a sub-critical barrier for comparison to sealing barriers. The main objective of this paper is to reveal the influencing factors of the leakage and breakdown mechanism when the dominant leakage path is through the bulk dielectric. The barrier integrity was modulated from sealing barrier conditions to sub-critical layers while keeping the same optimized integration interfaces.

B4.4.2

EXPERIMENTAL DETAILS The test