Explicit Threshold Voltage Modeling Insight for Short Channel Characterization of a WFE Elliptical GAA Strained-Si MOSFE
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https://doi.org/10.1007/s11664-020-08503-1 Ó 2020 The Minerals, Metals & Materials Society
Explicit Threshold Voltage Modeling Insight for Short Channel Characterization of a WFE Elliptical GAA Strained-Si MOSFET PRIYANKA SAHA
1,2
and SUBIR KUMAR SARKAR1
1.—Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700032, India. 2.—e-mail: [email protected]
This paper presents explicit analytical modeling of a gate all around (GAA) strained silicon metal-oxide-semicondutor field-effect transistor (MOSFET) with elliptical cross section by incorporating the popular gate work function engineering (WFE) concept of lateral mole fraction variation from source to drain end. Surface potential and threshold voltage formulation of the proposed structure based on a quasi-three-dimensional scaling equation have been introduced. The derived model is further used to investigate the short channel characteristics of the device in terms of hot carrier effect (HCE), drain-induced barrier lowering (DIBL), threshold voltage roll off (TVRO), and subthreshold slope. The impact of device parameter variation including gate oxide thickness, effective radius, channel doping concentration, germanium (Ge) mole fraction variation in the strained silicon channel along with applied gate to source and drain biases are evaluated on device performance to justify its efficiency in comparison to its single gate material (SM) MOSFET equivalent. Our analytical analysis is further validated by ATLAS-3D device simulated data to verify the precision of the derived model. Key words: Gate-all-around MOSFET, elliptical, threshold voltage roll off, DIBL, dual gate material, work function engineering, strained silicon channel
INTRODUCTION In recent years, device downscaling has been endorsed consistently for improving the performance of ultra low power circuits by achieving the requirements of high speed operation, low power consumption along with cost effective and miniaturized devices.1 However, the major bottlenecks associated with this scaling technology include unwanted short channel effects such as draininduced barrier lowering (DIBL), threshold voltage roll off (TVRO), degraded subthreshold swing, and hot carrier effect (HCE) which worsen the overall functional competence of the nano-scaled devices.2,3 These emerging barriers pose a serious challenge to the implementation of such ultra-nanoscaled
(Received May 26, 2020; accepted September 21, 2020)
devices in very large scale integrated (VLSI) circuits. Hence, it is necessary to modify existing metal-oxide-semicondutor field-effect transistor (MOSFET) structures through the combination of multi-gate topology, gate work function engineering, lateral channel engineering and adoption of new architectures/technologies, that will effectively circumvent the undesirable short channel effects (SCEs) in the nanometre regime.4–8 The structural standpoint reveals that among the existing multi gate geometries of single gate (SG), double gate (DG) and trigate (TG), a gate-
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