Impact of the High-Temperature Process Steps on the HfAlO Interpoly Dielectric Stacks for Nonvolatile Memory Application
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1071-F02-05
Impact of the High-Temperature Process Steps on the HfAlO Interpoly Dielectric Stacks for Nonvolatile Memory Applications Daniel Ruiz Aguado1,2, Bogdan Govoreanu1, Paola Favia1, Kristin De Meyer1,2, and Jan Van Houdt1 1 IMEC, Kapeldreef 75, Leuven, 3001, Belgium 2 K. U. Leuven, Kasteelpark Arenberg 10, Leuven, 3001, Belgium ABSTRACT This work reports on the performance of different Hafmiun aluminate (HfAlOx)-based interpoly dielectrics (IPD) for future sub-45nm nonvolatile memory (NVM) technologies. The impact of the thermal budget during the fabrication process is studied. The good retention and large operating window shown by this material, can be compromised by a high temperature activation anneal (AA) after the gate deposition. The AA step may induce phase segregation of the HfAlOx and outdiffusion of the Hf (Al) towards the floating gate/IPD and IPD/gate interfaces and subsequent formation of Hf (Al) silicates. These findings are supported by the low field leakage analysis, which shows large device to device dispersions. However, the effect of the spike anneal can be minimized if the HfAlOx layer is crystallized prior to the AA. Devices with polysilicon or TiN gate are compared in terms of memory performance and reliability. INTRODUCTION Scaling Flash memory technology to sub-45nm nodes requires cell planarization; hence a considerable reduction of the electrical thickness of the IPD is required in order to compensate for the loss of the sidewall coupling capacitance. This is achievable by combining high-k IPD’s with high-work-function metal gates [1-3]. When used as IPD, HfAlOx shows a large program/erase (P/E) window, while keeping the operating voltages at acceptable levels. Moreover, a good room temperature (RT) retention was observed for very thin layers, of only 12 nm physical thickness, with 0.5V window closure after more than 106s. This work reports on the impact of the thermal budget during the fabrication process on the performance of different HfAlOx-based IPD’s. The impact on performance of the gate material is also discussed. The paper is organized as follows: in the second section, a description of the test structures, review of the process flow and summary of the studied samples is given. The third section discusses the electrical results, focusing on retention ability of the IPD’s stacks, as well as on their physical characterization.
TEST STRUCTURES The test structures are fabricated in a process that allows formation of both floating gate capacitors and IPD capacitors on the same wafer. The floating gate capacitors have 8.5nm thermal SiO2 tunnel oxide (TO) grown on p-type Si substrate and a floating gate (FG) of n+ poly-Si formed by in-situ P-doping, on top of the oxide. The IPD stack is formed on top of the floating gate (FG), following a chemical-mechanical polishing (CMP) of the poly-Si film. This stack consists of a thin (~1nm) SiO2 interface and a 12nm layer of HfAlOx (high-k layer) formed by atomic layer deposition (ALCVD) with an Al2O3:HfO2 deposition cycle ratio of 1:1.
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