Low Voltage and High Speed Silicon Nanocrystal Memories
- PDF / 277,040 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 72 Downloads / 192 Views
D1.9.1
Low Voltage and High Speed Silicon Nanocrystal Memories Josep Carreras, B. Garrido, J. Arbiol and J. R. Morante EME, Electronics Department, University of Barcelona Carrer Martí i Franqués, 1, 08028 Barcelona, Spain
ABSTRACT We have studied a set of MOS cell structures with 30 nm thick thermal oxide implanted with Si at high doses (10, 15 and 20 atomic % at projected range) in which Si nanocrystals (Si-nc) have been precipitated by annealing at 1100 ºC. Energy filtered transmission electron microscopy reveals: i) a central layer of Si-nc with a mean size of 2.8 nm; ii) a control oxide of 12.5 nm completely free of Si-nc and iii) a tunnel oxide of about 2.5 nm. This narrow tunnel oxide enables the direct tunnel for charging and discharging which is a must for high speed and good reliability. However, this results in typical retention times ranging from only few hours to several months, depending on the concentration of Si-nc. For developing low voltage memories we have focused on the highest Si excess sample, which shows fast write times (tens of µs) at very low gate fields (±2 MV/cm or ±6V). The onset of Fowler-Nordheim conduction is of about ±6 MV/cm by J-V measurements (±18V), which means that the structure works in a direct tunnel regime. To increase the retention time we have performed an additional annealing step in diluted O2 for 16 and 32 minutes, resulting in a dramatic increase in the retention times, which is attributed to the re-growth of an additional tunnel oxide which eliminates surface roughness, remaining Si excess and defects at the Si-SiO2 interface. This additional oxidation step produces also a decrease in the mean size of the Si-nc distribution. Thus, we increase the retention time beyond the 10 years standard limit. Finally, the writing times can be traded-off by increasing slightly the program voltage up to ±2.7 MV/cm or ±8V.
INTRODUCTION Non-volatile memories (NVMs) with Si nanocrystals (Si-nc) as storage nodes have been recently proposed as candidates to keep on with the scaling trend of flash devices [1]. The high compatibility of Si-nc production with standard CMOS processing makes Si-nc memories suitable for manufacturing on an industrial scale. A continuous floating gate (i.e. polysilicon gate) embedded in a MOS structure has some limitations that can be overcome by replacing it by Si-nc embedded in the gate oxide. The Si-nc are used as charge storing elements which screen the gate electric field and change the flat-band voltage of the MOS structure. Some remarkable advantages of Si-nc NVMs are [2]: i) the non-continuity of the layer prevents from charge loss through lateral paths; ii) thinner tunnel oxide results in small write times at lower injection voltages and iv) reliability of the tunnel oxide is improved as charge is injected by direct tunnel and the existence of few defects do not compromise the whole structure. By using a p-type substrate, the write and erase states of the memory are obtained by injecting electrons or holes into the Si-nc, respectively.
D1.9.2
In
Data Loading...
