The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges
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The analog/RF performance of a strained‑Si graded‑channel dual‑material double‑gate MOSFET with interface charges Subba Rao Suddapalli1 · Bheema Rao Nistala1 Received: 4 May 2020 / Accepted: 19 August 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract The analog/radiofrequency (RF) performance of a strained-silicon (s-Si) graded-channel dual-material double gate (GCDMDG) metal–oxide–semiconductor field-effect transistor (MOSFET) with interface charges is investigated by using Sentaurus technology computer-aided design (TCAD) software. The analog/RF figures of merit of the proposed s-Si GC-DMDG MOSFET, including the intrinsic voltage gain, transconductance generation factor, early voltage, unity-current gain frequency ( ft ), transconductance–frequency product (TFP), gain–frequency product (GFP), and gain–transconductance–frequency product (GTFP), are evaluated for different values of device parameters such as the strain in the silicon, the interface charge density, and the thicknesses of the oxide and substrate layers. The simulation results exhibit that the proposed s-Si GCDMDG MOSFET device attains lower values of transconductance and output conductance and a higher value of early voltage compared with the s-Si graded-channel double-gate (GC-DG) MOSFET. Besides, the proposed s-Si GC-DMDG MOSFET device provides better performance in terms of ft , TFP, GFP, and GTFP in comparison with the s-Si GC-DG MOSFET in the strong inversion region, and vice versa in the subthreshold region. Keywords Center channel potential · Early voltage · Interface charges · Strained Si · Short-channel effects · Transconductance
1 Introduction Generally, strained-silicon (s-Si) MOSFETs exhibit improved electrical characteristics such as carrier mobility, carrier velocity, and drive current when compared with conventional silicon MOSFETs [1–6]. By using the layer transfer technique [7], strain is introduced into the silicon channel. In this technique, biaxial tensile strain is introduced into the silicon layer by growing a thin silicon layer on a relaxed Si(1−X) Ge(X) buffer layer that is developed on a silicon-oninsulator (SOI) substrate. Finally, by means of a selective etching process, the thin silicon layer is transferred onto the top of the buried oxide layer of the SOI substrate by removing the Si(1−X) Ge(X) layer. Consequentially, the strain in the silicon layer becomes a function of X (the Ge mole fraction) * Subba Rao Suddapalli [email protected] Bheema Rao Nistala [email protected] 1
Department of ECE, NIT Warangal, Telangana, Hanamkonda 506004, India
of the relaxed Si(1−X) Ge(X) , as also seen for a silicon layer grown directly on a Si(1−X) Ge(X) junction [8]. The removal of the Si(1−X) Ge(X) layer does not affect the amount of strain in the silicon layer [9]. Many authors have investigated hot carrier effects (HCEs) in double-gate (DG) MOSFETs, which are attributed to acceptor-type (electron) or donor-type (hole) interface-trap generation at the gate oxide interface, which can be co
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