Threshold Voltage Shift Variation of a-Si:H TFTs With Anneal Time
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Threshold voltage shift variation of a-Si:H TFTs with anneal time A. Indluru1, S. M. Venugopal2, D. R. Allee2,3, and T.L. Alford1, 2,3 1 School of Mechanical, Aerospace, Chemical and Materials Engineering, Arizona State University, Tempe, Arizona 85287 2 Flexible Display Center, Arizona State University, Tempe, Arizona 85287 3 School of Electrical, Computer, and Energy Engineering, Tempe, Arizona 85287
ABSTRACT Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used in many areas and the most important application is in active matrix liquid crystal display. However, the instability of the a-Si:H TFTs constrains their usability. These TFTs have been annealed at higher temperatures in hope of improving their electrical performance. But, higher anneal temperatures become a constraint when the TFTs are grown on polymer-based flexible substrates. This study investigates the effect of anneal time on the performance of the a-Si:H TFTs on PEN. Thin-film transistors are annealed at different anneal times (4 h, 24 h, and 48 h) and were stressed under different bias conditions. Sub-threshold slope and the off-current improved with anneal time. Off-current was reduced by two orders of magnitude for 48 hours annealed TFT and sub-threshold slope became steeper with longer annealing. At positive gatebias-stress (20 V), threshold voltage shift (∆Vt) values are positive and exhibit a power-law time dependence. High temperature measurements indicate that longer annealed TFTs show improved performance and stability compared to unannealed TFTs. This improvement is due to reduction of interface trap density and good a-Si:H/insulator interface quality with anneal time. INTRODUCTION Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) is the dominant switching element in active matrix liquid crystal displays (AMLCD) and also used in pixel circuits of organic light emitting displays (OLED). [1-4] There is a considerable industrial interest in exploring the performance of the low temperature fabricated TFTs on polymer substrates for flexible applications. However, the low temperature fabricated TFTs produce a substantial amount of defects in a-Si:H layer and the insulator compared to TFTs fabricated at standard temperatures on glass substrate. [5-6] Fabricating low-leakage insulators with low defect density a-Si:H layer at low temperatures is a great challenge. The most important drawback of a-Si:H TFTs is the thresholdvoltage shift (∆Vt) as a result of prolonged application of gate-bias stress. The trapped charge in the insulator and the defect creation in the a-Si:H layer are two main reasons for threshold voltage shift. It is important to minimize these defects in the TFTs for better performance. Annealing at elevated temperatures and high temperature deposition can be an option to improve the performance of the TFTs. [5-9] However, high anneal temperatures become a constraint when the TFTs are grown on polymer-based flexible substrates, as they are sensitive to high temperatures
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