Dual Material Gate Engineering to Reduce DIBL in Cylindrical Gate All Around Si Nanowire MOSFET for 7-nm Gate Length
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HYSICS OF SEMICONDUCTOR DEVICES
Dual Material Gate Engineering to Reduce DIBL in Cylindrical Gate All Around Si Nanowire MOSFET for 7-nm Gate Length Sanjaya,*, B. Prasada, and Anil Vohraa a Electronic
Science Department, Kurukshetra University, Kurukshetra, Haryana, 136119 India *e-mail: [email protected] Received July 6, 2020; revised July 6, 2020; accepted July 17, 2020
Abstract—In this work, drain current ID for 7-nm gate length dual-material (DM) cylindrical gate all around (CGAA) silicon nanowire (SiNW) has been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. In this device, we consider the non-equilibrium Green’s function (NEGF) approach and selfconsistent solution of Schrödinger's equation with Poisson’s equation. The splitting of conduction in multiple sub-bands has been considered and there is no doping in the channel region. The effect of DM gate engineering (variation of screen gate and control gate length having different work function) for SiNW channel with 2-nm radius and gate oxide (SiO2) thickness of 0.8 nm on ID have been studied. It was found that DM gate engineering reduces drain-induced barrier lowering (DIBL) but it also slightly increases sub-threshold slope (SS). This work has obtained small DIBL (~54 mV/V), small SS (~68 mV/dec), and higher IOn/IOff (~4 × 108) ratio as compared to literature concerning the inversion mode devices. The smallest DIBL is obtained when control gate length is the highest, and vice versa. With increase in control gate length, there is also increase in both IOn and IOff but IOn/IOff ratio decreases. Keywords: NEGF, DM CGAA, inversion mode, SiNW, ID, DIBL, SS DOI: 10.1134/S1063782620110111
1. INTRODUCTION Scaling of MOS transistor continues to get smaller and faster device. This downsizing follows the Moore’s law even after 5 decades. However, this miniaturization below 32-nm technology node faces challenge because of short-channel effects (SCEs), which are threshold voltage (VTh) roll-off, drain-induced barrier lowering (DIBL), and sub-threshold slope (SS) degradation. This problem is solved by using novel device structure such as double-gate (DG), trigate (FinFET), and GAA that have better electrostatic integrity over bulk MOSFET and also scale down to smaller gate length [1–4]. For 22-nm technology node, Intel used FinFET in 2011 [4]. But below 10-nm technology node, GAA is leading structure due to its superior electrostatic control over channel charge because of increased number of equivalent gates and is also more immune to SCEs as compared to other structure [5]. Hence dual-material (DM) CGAA with SiNW is the best solution and has been presented in this work. To continue with scaling, thickness of SiO2 has been continuously decreasing to increase the coupling between gate and the channel charge, to suppress SCEs and also to increase drain current ID, which is the main requirements of high-speed device [6]. Various important parameters depend upon the device
structure, gate material work function and channel length [7, 8].
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