Seedless Templated Growth of Hetero-Nanostructures for Novel Microelectronics Devices
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1178-AA04-04
SEEDLESS TEMPLATED GROWTH OF HETERONANOSTRUCTURES FOR NOVEL MICROELECTRONICS DEVICES F.Iacopi1, R.Rooyackers1, R.Loo1, W.Vanherle1, A.Milenin1, K.Arstila1, A.Verhulst1, S.Takeuchi1,2, H.Bender1, M.Caymax1, T.Hantschel1, A.Vandooren1, P.M.Vereecken1, S.De Gendt1,3, M.Heyns1,4 1
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; Physics Dept., Katholieke Universiteit Leuven, Belgium; 3 Chemistry Dept., Katholieke Universiteit Leuven, Belgium; 4 Metallurgy and Materials Engineering Dept., Katholieke Universiteit Leuven, Belgium. 2
ABSTRACT The feasibility of a templated seedless approach for growing segmented p-i-n nanowires –based diodes based on selective epitaxial growth is demonstrated. Such diodes are the basic structure for a Tunnel Field Effect Transistor (TFET) device. This approach has the potential for being easily scalable at a full-wafer processing, and there is no theoretical limitation for the control of nanowires growth and properties when scaling down their diameters, as opposed to an unconstrained vapor-liquid-solid growth. Moreover, Si/SixGe1-x hetero-structures are implemented, showing that this can improve the TFET ON current not only due to the lower barrier for the band-to-band source-channel tunneling, but thanks additionally to its lower thermal budget for growth, allowing for better control of the abruptness of the doping profile at the source-channel tunneling interface. INTRODUCTION The unconstrained Vapour-Liquid-Solid (VLS [1,2,3]) growth is a widely demonstrated method for growing a large variety of semiconductor nanowires. However, there are at least two main limitations for the application of such growth method in the wafer –scale manufacturing of nanowires –based devices for microelectronics. The first is linked to the catalyst type. The vast majority of the work reported in literature so far makes use of Au as the metal catalyst. Au is an undesired metal for Si –based devices, as Au diffusion into Si would lead to the creation of mid- band recombination centers, with detrimental consequences on device performance [4]. Although reports on the actual impact of Au impurities in Si nanowires are contradictory [5,6], the use of Au is not allowed in silicon manufacturing processes. We have previously demonstrated that this limitation for the growth of Si nanowires could be overcome with the use of In catalyst particles, in combination with a Plasma Enhanced Chemical Vapour Deposition growth system [7]. However, additional problems with scalability due to the solubility changes and additional limitations for catalyst particles of a few nm size should still be dealt with [8,9]. Some other groups have proposed an uncatalyzed growth approach [10]. The second limitation concerns the control on the growth orientation of the wires with respect to the substrate. This is critical for the subsequent processes needed for the full
wafer –scale integration of such nano-structured building blocks in microelectronic components. In an unconstrained VLS growth, this control relies onto the princi
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