Electrically Induced Junction MOSFET for High Performance Sub-50nm CMOS Technology
- PDF / 71,821 Bytes
- 6 Pages / 595 x 842 pts (A4) Page_size
- 95 Downloads / 163 Views
Electrically Induced Junction MOSFET for High Performance Sub-50nm CMOS Technology Abhisek Dixit, Rajiv O. Dusane1, V. Ramgopal Rao Department of Electrical Engineering, Indian Institute of Technology Bombay, Powai, Mumbai-400 076, India. 1 Department of Metallurgical Engineering and Materials Science, Indian Institute of Technology Bombay, Powai, Mumbai-400 076, India. ABSTRACT Degrading of short-channel effects (SCE) e.g. Drain-Induced-Barrier-Lowering (DIBL), charge-sharing etc., as CMOS devices are scaled into the sub-50nm regime, is a major roadblock for ULSI technologies. This problem can be circumvented to some extent by a proper scaling of MOSFET vertical dimensions (junction depths, oxide thickness etc.). In this work we propose a novel implementation of an electrically induced junction (EJ) MOSFET. An EJ-MOSFET is different from conventional CMOS device in that the gate voltage electrically induces the shallow source-drain extensions (SDEs). In such a device the SDEs are underneath the gate and contain low-doped regions of opposite conductivity as that of deep source-drain (S/D). In order to turn ON the device, a voltage is applied at the gate of EJ-MOSFET device, such that these low doped regions below poly-Si gate get inverted and serve as SDEs. Consequently, the effective channel length in this condition is the distance between these low-doped regions. On the contrary, at any gate voltage less than that required for inverting these regions, no SDEs are induced, and the effective channel length is equal to the physical separation between the deep S/D junctions. INTRODUCTION With continuous scaling of sub-micron MOSFETs, controlling short-channel effects becomes the biggest challenge. Gate oxide thickness, S/D junction depth, channel doping etc. need to be scaled in order to maintain a good short-channel performance in sub-50nm MOSFETs. Though all of these approaches are currently being followed in order to control the short-channel effects, the degradation in the overall device performance and power dissipation becomes unacceptable as one enters the sub-50 nm CMOS technology regime. Scaling of junction depth increases the series resistance, affecting the drive currents, while a scaling of gate oxide thickness with SiO2 leads to high leakage currents. Increased channel doping concentration increases the transverse fields, as well as degradation in mobility. Also scaling of threshold voltage (VT) below a certain value (say, VDD/3) is not desirable from the circuit point of view, as it leads to weak turn-off of the transistors. Attempts to adjust VT by gate-stack engineering are also being made but they require incorporation of additional process steps as well as new materials in the conventional CMOS fabrication process. In order that the sub-50nm devices meet the performance criterion, alternative methodologies for controlling the SCE need to be developed. The concept of Electrically Induced Junction MOSFET has been illustrated earlier by a few researchers [1]. It has been shown to replace shallow source-
Data Loading...
