Comparative Study of Single and Double Gate All Around Cylindrical FET Structures for High-K Dielectric Materials
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Transactions on Electrical and Electronic Materials https://doi.org/10.1007/s42341-020-00258-0
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Comparative Study of Single and Double Gate All Around Cylindrical FET Structures for High‑K Dielectric Materials Rajveer Kaur1 · Balwinder Singh1 Received: 2 February 2020 / Revised: 9 October 2020 / Accepted: 2 November 2020 © The Korean Institute of Electrical and Electronic Material Engineers 2020
Abstract The performance of conventional MOSFET deteriorates because of the short channel effects that appears when it is scaled into nm regime. The existing techniques like channel scaling, variations in the work function implemented on a MOSFET could no longer confront these limitations which demand for the necessity of some upgraded devices and materials that would overcome these shortcomings and offer ameliorate performance. Two experimentally based devices gate all around (GAA) FET and double gate all around (DGAA) FET are modeled and compared at 10 nm and 20 nm respectively In this paper, the effect of scaling the gate length, oxide thickness and variations in the drain to source voltage utilizing two different gate dielectrics for a single and double GAA cylindrical FET on their respective device performance in terms of drive current (ION), leakage current (IOFF), switching speed ( ION/IOFF) and subthreshold swing. The study reveals that with a thinner gate oxide, less gate length, less drain to source voltage and with an additional core gate utilizing high-k dielectric materials, the device achieves a better subthreshold slope, higher value of ON-state current, larger ON/OFF current ratio, lesser OFF-state current and lesser power consumption. Keywords CMOS · MOSFET · Gate all around (GAA) FET · Double gate all around (DGAA) FET · Short channel effects · On current · Off current · Scaling
1 Introduction Transistor comes into existence in early 1960s plays an essential role in the semiconductor industry. High speed, less area and low power consumptions in the portable devices become the primary concern for researchers in the semiconductor industry [1]. The reduction in the dimensions of a planar CMOS is a cumbersome task. The reduction in the dimensions of a planar CMOS provide better performance and excels the functionality of conventional MOSFET (CMOS) but scaling in nm regimes becomes a cumbersome task. It has an inferior impact on the gate control over the channel which is the main reason for performance degradation of the device as it suffers from short channel effects such as mobility degradation, variations in the threshold voltage (Vth), increase in the leakage current and difficulty in increasing the ON-current [1]. According to International * Balwinder Singh [email protected] 1
ACS Division, Centre of Development of Advanced Computing, Mohali 160071, India
Technology Roadmap for Semiconductor (ITRS) roadmaps (2015) given by Semiconductor Research Corporation, the electronics industry will reach its fundamental limit by 2020s [2, 3]. The number of transistors in a single IC has a
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