Impact of Annealing on the Resistivity of Ultrafine Cu Damascene Interconnects
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Impact of Annealing on the Resistivity of Ultrafine Cu Damascene Interconnects G. Steinlesberger1, 2, M. Engelhardt1, G. Schindler1, W. Steinhögl1, M. Traving1, W. Hönlein1, E. Bertagnolli2 1 : Infineon Technologies, Corporate Research, 81739 Munich, Germany 2 : Vienna University of Technology, 1040 Vienna, Austria Abstract The influence of different annealing conditions on the electrical resistivity of copper damascene interconnects with lateral dimensions down to sub-50 nm was studied. Different thermal treatments after copper plating as well as annealing processes in addition to the final anneal step were carried out in order to study the microstructural change of copper damascene lines. It was found that rapid thermal annealing (RTA) at high temperatures (600°C) leads to an enlargement of the Cu grains by a factor of 2 for wide lines, whereas a significant impact of annealing on the median grain size of ultrafine lines was not observed. This is attributed to the geometrical limitation of the grain growth process. As a result, the size effect in Cu nano-interconnects which is mainly determined by grain boundaries acting as scattering sites for electrons cannot be reduced significantly by using thermal treatments.
Resistivity [µΩ cm]
Introduction Efficient on-chip communication means high-speed signal transmission with minimal propagation delay. As technology scales down to smaller dimensions an increasing disparity between gate and interconnect signal delay (τ=RC) appears. Besides the conductor geometry the RC product depends on the properties of the intermetal dielectric (IMD) and the conductor material: the dielectric constant k and the electrical resistivity ρ. In this work in particular the electrical resistivity of ultrafine Cu damascene lines for application in future metallization systems is studied. If electrical current flows, charge 6.0 carriers are scattered at internal and external surfaces and 5.0 Scattering at internal interfaces on their way through a Combination surfaces (I) polycrystalline metal conductor. 4.0 of (I) + (II) Due to electron scattering effects Scattering the electrical resistivity increases 3.0 at external with shrinking line dimension. surfaces (II) 2.0 This is known as size effect in thin Cu lines /1-4/. A physical ρ (Cu bulk) 1.0 model, which combines both Experimental Data electron scattering effects at 0.0 internal and external scattering 10 100 1000 sources, was developed in order wLine [nm] to interpret the electrical size effect in interconnects. The key Fig. 1: Electrical resistivity of Cu damascene lines with parameters are p, the probability different lateral dimensions down to 43 nm. A physical model of specular scattering at the combining scattering effects at internal (I) and external (II) surfaces is in excellent agreement with the experimental data. surface, λ, the mean free path of
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