Molybdenum as a Gate Electrode for Deep Sub-Micron CMOS Technology
- PDF / 322,854 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 11 Downloads / 158 Views
MOLYBDENUM AS A GATE ELECTRODE FOR DEEP SUB-MICRON CMOS TECHNOLOGY Pushkar Ranade†, Yee-Chia Yeo, Qiang Lu, Hideki Takeuchi, Tsu-Jae King, Chenming Hu Department of Electrical Engineering and Computer Sciences † Department of Materials Science and Engineering University of California at Berkeley, Berkeley, CA 94720
ABSTRACT: Molybdenum has several properties that make it attractive as a CMOS gate electrode material. The high melting point (~2610°C) and low coefficient of thermal expansion (5×10-6/ ºC, at 20 ºC) are well suited to withstand the thermal processing budgets normally encountered in a CMOS fabrication process. Mo is among the most conductive refractory metals and provides a significant reduction in gate resistance as compared with doped polysilicon. Mo is also stable in contact with SiO2 at elevated temperatures. In order to minimize short-channel effects in bulk CMOS devices, the gate electrodes must have work functions that correspond to Ec (NMOS) and Ev (PMOS) in Si. This would normally require the use of two metals with work functions differing by about 1V on the same wafer and introduce complexities associated with selective deposition and/or etching. In this paper, the dependence of the work function of Mo on deposition and annealing conditions is investigated. Preliminary results indicate that the work function of Mo can be varied over the range of 4.0-5.0V by a combination of suitable postdeposition implantation and annealing schemes. Mo is thus a promising candidate to replace polysilicon gates in deep sub-micron CMOS technology. Processing sequences which might allow the work function of Mo to be stabilized on either end of the Si energy band gap are explored. 1. INTRODUCTION: According to the 1999 edition of the International Technology Roadmap for Semiconductors (ITRS)[1], continued scaling of CMOS devices beyond the 100nm technology node (2002) will rely on fundamental changes in transistor gate stack materials. Current research is being driven by the search for post-SiO2 gate dielectrics. The replacement of SiO2 with high-κ gate dielectrics (metal oxides, metal silicates, etc.) will also necessitate the use of gate electrode materials (other than the conventional dual-doped polysilicon) that form thermodynamically stable interfaces with the dielectric. Also driving the change to alternative gate electrodes is the growing need for tighter threshold voltage control and lower gate resistivity in short channel CMOS devices. The most promising alternative gate electrode materials are thus likely to be metals or their immediate derivatives (nitrides, silicides, etc.). The flexibility afforded by the use of polysilicon as a gate electrode material is immense. The relative ease with which the work function of polysilicon can be selectively modified on a wafer precludes the need to deposit/etch two different gate electrode materials. It is evident that this flexibility will be lost in moving to metal gate electrodes (unless mid-gap metal electrodes are used). Dual metal gate CMOS technology has been
Data Loading...
