A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era
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A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano‑Scale Era Harekrishna Kumar1 · V. K. Tomar1 Accepted: 5 November 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract The growing demand of Internet of things based portable gadgets motivate to develop low power static random access memory (SRAM) cell. It occupies large portion in modern system on chip devices. In this context, a detailed review on various SRAM cell topologies has been performed which includes comparative analysis of design parameters and challenges. To perform the comparative analysis, considered SRAM cell topologies are simulated with cadence virtuoso IC6.1.5-64b at 45 nm generic process design kit technology file. It is worthy to notice that 9T SRAM cell has highest value of read stability among considered cells. It is attributed to use of differential read decoupled structure. The 7T SRAM cell has highest value of write ability among considered cells. It is observed that 8T SRAM cell has lowest read power dissipation among considered cells. It happens due to the use of stack transistor in read path of the cell. The lowest value of read access time is also observed in 8T SRAM cell among considered SRAM cells. It is 1.82× higher as compared to conventional 6T SRAM cell. Further, the write access time of 9T SRAM cell is lowest among considered cells. This is 1.41× less as compared to conventional 6T SRAM cell. Static noise per unit area to power delay product ratio (SAPR) is used to evaluate the overall performance of considered SRAM topologies. It is observed that 8T SRAM cell has the highest value of SAPR among considered SRAM cells. It is 1.91× as compared to conventional 6T SRAM cell. All the comparison has been done at 1.0 V supply voltage. Keywords Low-power · Stability · Access time · Leakage current · Ion ∕Ioff ratio
1 Introduction Now a day’s, high performance integrated circuits are being implemented in deep submicron technology [1]. Abundant work has been carried out in the design and development of portable devices for emerging applications such as implanted medical equipments, wireless body sensing networks, space applications [2], etc. These applications call for the design of low power semiconductor memory devices. Conventional 6T static random access memory (Conv.6T SRAM) covers a substantial part of a system-on-chip * Harekrishna Kumar [email protected] 1
Department of Electronics and Communication Engineering, GLA University, Mathura, India
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area and controls the whole system performance. As technology gets shrink, power dissipation becomes the prominent factor that degrades the battery backup of the portable device. The reduction in supply voltage is a popular method to reduce the power dissipation of SRAM cell at the cost of degradation in performance. Numerous researchers have proposed various SRAM cell topologies such as 7T [3], 8T [4], 9T [5], and 10T [6] to enhance the performance and stability with an inc
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