Design of differential TG based 8T SRAM cell for ultralow-power applications
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TECHNICAL PAPER
Design of differential TG based 8T SRAM cell for ultralow-power applications Chandramaulashwar Roy1 • Aminul Islam1 Received: 7 January 2018 / Accepted: 8 July 2018 Ó Springer-Verlag GmbH Germany, part of Springer Nature 2018
Abstract Low power cache memory in a system on chip is in high demand today. With the lowering of MOSFET’s channel length, low-power SRAM design has become a more challenging task. This paper presents differential 8T SRAM cell with minimum power utilization. The proposed cell has one pair of transmission gate as access switches. Due to use of TG instead of pass gate access transistor its write access time (TWA) is short. The low power consumption of the cell is due to stacking effect. This paper compares design metrics of the proposed cell with conventional 6T (CON6T) and ZIGZAG 8T (ZG8T) SRAM cells. The proposed 8T SRAM cell shows 1.159/1.179 improvement in TWA as compared to CON6T/ ZG8T at a penalty of 2.659/29 in read access time (TRA). The proposed cell consumes 3.229 less hold power compared to both CON6T and ZG8T SRAM cells. And the proposed cell consumes 4.419 (4.449) less write power as compared to CON6T (ZG8T) SRAM cell. Our proposed cell takes 1.379 lower chip area as compared to ZG8T cell at the expense of 1.499 higher area as compared to CON6T SRAM cell. The proposed cell also achieves 1.59/39 higher stability during write operation as compared to CON6T/ZG8T SRAM cell, respectively. Read static margin of the proposed cell is same as CON6T but 3.29 lower than ZG8T SRAM cell.
1 Introduction Low power static random access memory (SRAM) design is very important for devices like self-powered wireless sensor, energy harvesting equipments, some instrument which is used in biomedical applications like pacemaker, pedometer, hearing-aid etc., in which battery life is prime factor (Chen et al. 2010; Chandrakasan et al. 2008; Sridhara et al. 2011). Portable devices like laptop, cell phone etc., also need a processor with low power consuming SRAM. At present, almost all digital systems and highperformance processors use SRAM as level1 (L1), level2 (L2) and level3 (L3) cache memory. Emerging applications, like implanted medical instruments, wireless body sensing network and bioelectronics devices demand power efficient SRAM. According to ITRS 2013, 90% of total area of a network on chip (NoC) or System on chip (SoC) is acquired by SRAM & Chandramaulashwar Roy [email protected] 1
Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University) Mesra, Ranchi, Jharkhand, India
cells (SIA (2013), ITRS. 2011 Edition. http://www.itrs2.net/ itrs-reports.html). As SRAM occupies a large amount of area in any chip so it contributes a large portion of total power consumption. So, reducing power consumption is the main criteria in designing SRAM cell. There are various techniques to reduce power consumption of a circuit. Scaling down the supply voltage is the best way to minimize power consumptio
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