Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-su
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Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET‑on‑SELBOX‑substrate Ashish Kumar Singh1 · Manas Ranjan Tripathy1 · Kamalaksha Baral1 · Prince Kumar Singh1 · Satyabrata Jit1 Received: 31 March 2020 / Accepted: 30 July 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract This paper reports the TCAD based investigation of the DC/RF and linearity characteristics of a newly proposed dualmaterial (DM) laterally-stacked (LS) S iO2/HfO2 heterojunction-TFET-on-SELBOX substrate (LS-STFET). Device-level performance comparison is made between the proposed TFET with a dual-material (DM) vertically-stacked (VS) SiO2/HfO2 heterojunction-TFET-on-SELBOX substrate (VS-STFET). Low bandgap material Ge is used in the source region to form a Ge (source)/Si (channel) heterojunction for enhancing the ON-state current of the presented TFETs. The effects of both donor (+ ve) and acceptor (−ve) type interface trap charges at the channel/SiO2 region on the DC, analogue/RF and linearity figure of merits have been analyzed for both the devices under study. The LS-STFET is shown to possess higher ON-state current and smaller subthreshold swing (SS) over the VS-STFET. In addition, the LS-STFET is shown to have better DC, analog/ RF and linearity performance over VS-STFET in the presence of the donor and acceptor interface trap charges. Keywords Band-to-band tunneling (BTBT) · Tunnel field-effect transistor (TFET) · Heterojunction · Selective buried oxide (SELBOX) · Interface trap charge (ITC)
1 Introduction The dimension scaling of MOSFETs has just come to its bottleneck because of intense short-channel-effects (SCEs) in sub-50 nm gate lengths [1]. As a result, researchers have invested several non-classical MOSFET structures like the junction less MOSFETs [2], Nanowire FETs [3], carbon nanotube FETs [4], negative capacitance FETs [5], tunnel FETs [6], etc. to achieve smaller SCEs in sub-50 nm gatelengths. Among them, Tunnel FETs (TFETs) have drawn considerable attention due to their possibility of having the subthreshold swing (SS) below the Boltzmann limit of 60 mV/dec in bulk MOSFETs, extremely small IOFF current, and a very high ION/IOFF ratio [6]. Unlike the surface inversion in the bulk MOSFETs, the TFET works on the principle of band-to-band tunneling (BTB) phenomenon. The device can be viewed as a gated p-i-n diode operated under reverse bias where the drain current is resulted from tunneling of carriers from the valence band of the source (i.e. p-region)
* Satyabrata Jit [email protected] 1
IIT(BHU), Varanasi, Uttar Pradesh, India
to the conduction band of the channel (i.e. i-region) [7, 8] followed by drifting of these carriers from the channel to the drain (i.e. n-region). However, the major problem of the TFET is its inherently poor ON-state current which restricts its application in the IC technology. Various structural modifications such as the use of source/channel heterojunction (HJ) [9], dual-material (DM) [10], high-k gate oxide [8
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