Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features
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0913-D02-02
Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features Claude Ortolland1,2, Pierre Morin3, Franck Arnaud3, Stephane Orain1, Chandra Reddy4, Catherine Chaton5, and Peter Stolk1 1 Philips Semiconductors, 860, rue Jean Monnet, Crolles, Isere, 38926, France 2 Laboratoire Physique de la Matirère, 7, Avenue Jean Capelle, Villeurbanne, Rhone, 69621, France 3 ST Microelectronics, 850, rue Jean Monnet, Crolles, Isere, 38926, France 4 Freescale Semiconductor, 870, rue Jean Monnet, Crolles, Isere, 38926, France 5 CEA-LETI, 850, rue Jean Monnet, Crolles, Isere, 38926, France ABSTRACT In this paper the impact of process-induced stress and transistor layout on device performance in state-of-the-art 65nm CMOS technology has been studied. We have focused this analysis on different nitride liners above devices (Contact Etch-Stop Layers – CESL) which have been fabricated on two differently oriented (100) substrates: and . This overview permits to have a good understanding of CESL, and to choose the right strategy in terms of process induced stress in future microelectronic technologies. INTRODUCTION Recent publications have shown the advantages of CESL [1] techniques to boost intrinsic MOS transistors performance. It is well known that performance enhancement is achieved on nMOS with tensile film whereas on pMOS with high compressive layers [2]. Moreover, substrate orientation engineering proves that channel enhances pMOS drive current without significant effect on nMOS [3] & [4]. It has been demonstrated that thickness, intrinsic stress and Sidewall Step Coverage (SSC) are important material parameters to reach the highest mobility enhancement for different devices [5]. In this paper, an analysis of CESL and substrate orientation on device properties is presented. A specific attention has been paid to relate the performance gain to the active layout and transistor dimension. In addition CESL nitride layers grown by Plasma Enhance Chemical Vapour Deposition (PECVD) and Atomic Layer Deposition (ALD) are compared. EXPERIMENTAL DETAILS A conventional 65nm process flow has been integrated on (100) bulk substrates with a 0.3µm STI depth and with either or current flow orientation. A 1.8nm oxynitride and 100nm of poly thickness compose the Gate stack. NiSi is used as salicide. The purpose is to investigate the layout parameters which modulate the CESL effect on transistor performance. The set of nitride experiments is described by table I and II. Different nitride processes for Tensile CESL have been compared to determine the key material parameters.
Table I and II. Different nitrides used for CESL with PECVD Process (I: left table) and ALD process (II: right table). Sample Deposition Thickness Stress As Dep. [nm] [GPa] PECVD Temperature [°C] 1 400 33 1,1 2 400 35 1,2 3 400 47 1,2 4 400 58 1,2 5 400 81 1,2 6 400 35 0,5 7 400 35 0,9 8 400 50 0,9 9 480 35 0 10 480 50 0,75 11 480 35 0,75 12 480 120 0,75 13 480 35 1,2 14 480 50 1,2 15 400 50 1,5 16 400 50 -1,9
Sample Deposition Thickness Stress As D
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