Quantum Mechanical Effect on Trigate Junctionless FET for Fast Switching Application
- PDF / 1,658,320 Bytes
- 13 Pages / 439.37 x 666.142 pts Page_size
- 84 Downloads / 170 Views
Quantum Mechanical Effect on Trigate Junctionless FET for Fast Switching Application M. Prasad1 · U. B. Mahadevaswamy1 Accepted: 29 October 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract In this study, Trigate Junctionless FET device has been explored for its analog performance. The anolog and RF parameters for device performance like trans-conductance (gm), output conductance (gd), intrinsic gain (Av) and cut-off frequency (ft) are evaluated using visual TCAD tool. Simulation result reveals that a very low capacitance value (in the order of 10− 19 ) which minimises ON state delay and making the device suitable for fast switching applications. The AC analysis of device demonstrates quite high cut off frequency of 2.44 GHz and a remarkable transconductance (Gm) of 0.154 𝜇 S. Furthermore, a novel CMOS Inverter has been designed using TGJLFET device structure in NMOS and PMOS configuration. The DC and transient response of the same has been studied extensively. Keywords Trigate · Junctionless · N-type · P-type Classical · Quantum mechanical effects · AC–DC
1 Introduction In the CMOS technology with the use of high-k material in the gate dielectric which leads to reduce leakage current [1]. Gate all around Nanosheets and Nanowires offer more flexibility in terms of power and performance optimization and also offers more freedom to the designer to tune the device parameters [2]. To improve the performance of the device, the surface roughness should be minimum to avoid scattering [3]. With strong quantum mechanical confinement in the channel requires quantum correction, which leads to a considerable reduction in the saturation current [4]. And RC delay can be improved by providing a selective deposition method [5]. Surface orientation, channel directions, and thickness of the silicon are more important parameters in FinFETs [6]. RF/analog performance is improved by drain extension with dual-kk with underlap FinFET [7]. The adoption of the process-induced variation shows an increase in DC/AC performance and also improves the RC delay [8]. A small-signal model of an RF MOSFET with a simple and accurate * M. Prasad [email protected] U. B. Mahadevaswamy ubms‑[email protected] 1
ECE Department, Sri Jayachamarajendra College of Engineering, Mysuru, India
13
Vol.:(0123456789)
M. Prasad, U. B. Mahadevaswamy
parameter extraction is presented [9]. Short channel effects can be overcome by surface treatment for drain overlap regions and a vertical structure to maintain fine short channel characteristics [10]. High performance can be achieved by different shapes and miniaturization in Fin shape [11]. Further, the stacked Nanosheet device is a better solution for the replacement of FinFETs by attaining superior driving current and scalability with the same device area and it can achieve competitive circuits performance compared with FinFET and Nanowires [12]. Further, providing multi-threshold to NSFETs will satisfy a wide range from ultra-power to high-performance applications [13]
Data Loading...
