Stress Evolution and Notch Formation During Polysilicon Gate Electrode Etching
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Abstract We have developed a numerical simulation based on the boundary element method that models thermal contraction-induced stresses within semiconductor microstructures, and the effects of these stresses on surface evolution. The test case we have studied is that of polysilicon gate etch during over-etching in a plasma environment. We assume a local etch rate proportional to the normal component of the surface strain energy density gradient caused by the differential thermal contraction of polysilicon substrate and underlying silicon dioxide film. This leads to the prediction of stress-enhanced etching in the area near the polysilicon / gate oxide interface, where large stresses develop during cooling from deposition temperature to room temperature. It is proposed that stress-enhanced etching of this nature may be partially responsible for a common type of deleterious feature observed experimentally during gate electrode patterning known as "notching".
Introduction During the deposition and subsequent cooling of multi-layer film structures, such as transistor gate electrode stacks deposited on a silicon dioxide layer, large thermally induced stresses can develop due to the different thermal expansion coefficients of the films involved.
For example, in the simple case of a polysilicon gate layer deposited at high temperature on a thin gate oxide film and subsequently cooled, tensile stresses will develop in the polysilicon since the thermal expansion coefficient of polysilicon is greater that that of silicon dioxide. In the semiconductor processing industry such deposition and subsequent pattering procedures are important in many key fabrication steps. In the case of polysilicon films, a chlorinecontaining plasma is generally used to define the gate electrode by etching through the polysilicon layer with minimal etching of the underlying silicon dioxide gate dielectric. Recent experimental work by Nozawa and coworkers' has shown that a certain type of deleterious microfeature can form during overetching near the interface between the polysilicon gate electrode and the underlying silicon dioxide film. This phenomenon has been termed "notching", an example of which is shown in Figure 1.As can be seen in this scanning electron micrograph, a deep "notch" has formed near the foot of the etched gate electrode near the gate electrode / gate oxide interface. Note that the notch has propagated along the interface into the bulk of the gate electrode. The presence of notches is clearly undesirable and although device manufacturers have generally found ways to avoid their formation through empirical trial-and-error strategies, it is of considerable interest to understand why they form. As device dimensions shrink, microfeature shapes must meet increasingly strict tolerances, and it will be necessary to understand processes such as notch formation that affect shape evolution during processing. Until recently, the theoretical literature concerning this phenomenon has focused mainly on surface charging-related effects which
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