Schottky-Barrier Si Nanowire MOSFET: Effects of Source/Drain Metals and Gate Dielectrics
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1017-DD14-05
Schottky-Barrier Si Nanowire MOSFET: Effects of Source/Drain Metals and Gate Dielectrics Weifeng Yang, Sungjin Whang, Sungjoo Lee, Haichen Zhu, Hanlu Gu, and Byungjin Cho Silicon Nano Device Laboratory, ECE department, National University of Singapore, Singapore, 117576, Singapore ABSTRACT We fabricated and studied the performance of Schottky-Barrier Si nanowire FETs (SiNW FET) by using Vapor-liquid-solid (VLS) grown Au-catalyzed SiNWs (20 nm). These devices were formed on various gate dielectrics (HfO2 or Al2O3) with different metal Source and Drain (S/D) regions (Pd, Ni). P-type behavior was observed and high Ion/Ioff ratio (~105) was achieved from undoped SiNW FETs. Besides, no ambipolar transportation was observed in our devices performance. This is possibly due to the small schottky barrier height for hole carriers at Source sides formed by high work-function metal. Furthermore, low subthreshold slope as 68mV/decade was obtained from SiNW FETs integrated with Ni S/D and Al2O3 High-κ gate dielectric. INTRODUCTION Single crystal Si nanowire (SiNW) has attracted intensive research interests due to its unique one dimensional structure. Various nanowire synthesis methods [1-3] have been developed including vapor-liquid-solid (VLS) growth [4]. This method can provide large quantity of nanowires whose diameter is as thin as 20nm. Furthermore, SiNW-based FET [5, 6] has become one of the most competitive candidates in MOSFET technology to meet the aggressive CMOS scaling requirements. Nevertheless, many questions still remain, such as how to achieve the optimum ON current and conductance, higher ION/IOFF current ratios, lower subthreshold swing (S.S.), and highly scaled gate dielectrics and channels. Schottky Barrier S/D is one of the promising options for FET fabrication. Schottky Barrier MOSFETs have a number of advantages including simple and low temperature processing, smaller parasitic resistance, and the elimination of doping and subsequent activation steps. Besides, high work-function metal like Pd or Ni is believed to enhance the holes injection at S/D region due to its lower barrier height for Si valence bands. Better switch properties can also be achieved by using high-κ gate dielectrics. In this work, we demonstrate that single crystallized undoped SiNWs FETs with Schottky contacts and high-κ gate dielectric (HfO2 / Al2O3) can be used as high performance MOSFETs for future nano-scale devices.
EXPERIMENTAL DETAILS Au nano-particles catalyst (20 nm) was dispersed on Si substrate which was transferred into a cold wall Chemical-Vapor-Deposition (CVD) system. SiH4 gas (200 sccm) was flowed into the chamber with H2 (200 sccm) as carrier gas. The SiNW growth was carried out at ~ 440 °C. During the growth [7], total pressure was kept at 25 Torr. Figure 1 shows the cross sectional
SEM view of typical Si nanowires with ~10 µm length. TEM picture in figure 2 validates that grown SiNW is single crystallized with a diameter of 20 nm.
20 nm
Figure 1: SEM picture for grown undoped SiNW with Au catalyst in
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