Reactive Ion Etched MO/CR Source-Drain Metallization for Amorphous Silicon Thin Film Transistors
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REACTIVE
ION
ETCHED
MO/CR SOURCE-DRAIN METALLIZATION AMORPHOUS SILICON THIN FILM TRANSISTORS
R.F. KWASNICK, G.E. POSSIN, AND R.J. SAIA GE Corporate Research and Development, Schenectady, NY
FOR
12301
ABSTRACT A novel two step reactive ion etch (RIE) process is described for the etching of bilayer Mo/Cr source-drain metallization on hydrogenated amorphous silicon (a-Si:H) inverted-staggered thin film transistors. The Cr acts as an etch stop during Mo etching, and is thin enough (-30 nm) that only a small thickness of underlying a-Si is removed during the Cr etch. The resulting Mo/Cr profile is sloped, compared to the more vertical and somewhat uncontrolled slope that is achieved with Mo wet etch. Very similar transistor behavior was observed for both Mo wet etched and Mo/Cr reactive ion etched source-drain metallization. The major advantage of this process over wet etching of Mo source-drain is improved step coverage of subsequently deposited layers due to the less vertical sidewall slope. INTRODUCTION In general, wet etching is preferable to dry etching in large area processing because of its lower cost and higher throughput. Wet etching creates a sloped sidewall profile in amorphous dielectric layers, for example in silicon nitride deposited by plasma-enhanced chemical vapor deposition (PECVD) . However, the sidewall profile of wet etched sputter deposited Mo is often nearly vertical and sometimes even reentrant, in part because of the influence of the nearly columnar grain structure of the layer. Unfortunately, the low process temperatures associated with large area processing makes it is difficult to achieve low stress and conformal coating over steps. Thus, the slope associated with wet etching of amorphous films is desirable with respect to the problematic issue of the step coverage of subsequently deposited layers. Mo is well established as a good electrical contact material to n+ a-Si:H, and hence as the source-drain metal in thin film transistors (TFT's). In addition, sputtered Mo films [1] have a resistivity of about 10 microohm-cm, which is less than that of Cr. Because of the sidewall profile issue described above, it was decided to investigate dry etching as a way to improve the sidewall profile of Mo used as the source-drain metal on inverted-staggered TFT's. In inverted-staggered TFT's, the source-drain metal is patterned directly on top of the a-Si in the channel region (Fig. la) . The formation of the TFT is completed when the n+ a-Si region is etched away and the TFT is passivated (Fig. lb) . Clearly, the source-drain etch process must have excellent selectivity to the underlying a-Si for adequate process control. Additionally, the formation of a sloped profile in the source-drain is desirable, as discussed above. A sloped sidewall profile can be achieved in Mo by plasma barrel etching using, for example, CF4/02 or SF6/02 by varying the gas Mat. Res. Soc. Symp. Proc. Vol. 219. 01991 Materials Research Society
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TABLE 1 Mo/Cr Reactive Ion Etch Process Gas Etch Rates: (nm/min) Mo Photores
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