Effect of Channel Engineering on Quasi-Static Capacitance-Voltage Characteristics of Double-Gate MOSFET
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https://doi.org/10.1007/s11664-020-08307-3 Ó 2020 The Minerals, Metals & Materials Society
Effect of Channel Engineering on Quasi-Static CapacitanceVoltage Characteristics of Double-Gate MOSFET SANJAY
,1,2 B. PRASAD
,1,3 and ANIL VOHRA
1,4
1.—Electronic Science Department, Kurukshetra University, Kurukshetra, Haryana 136119, India. 2.—e-mail: [email protected]. 3.—e-mail: [email protected]. 4.—e-mail: [email protected]
The quasi-static capacitance–voltage (QSCV) characteristics of 10-nm-gatelength double-gate N-type metal–oxide–semiconductor field-effect transistors (NMOSFETs) with Si, Ge, InAs, In0:53 Ga0:47 As, and GaAs as channel materials are studied and simulated using Silvaco ATLAS three-dimensional (3D) technology computer-aided design (TCAD) software. The QSCV approach offers the advantage of immunity against frequency dependence effects and the ability to measure small capacitances in the 100 fF range. In this device, we consider the self-consistent solution of Schrodinger’s equation with Poisson’s equation. The splitting of the conduction band into multiple subbands is considered, while there is no doping in the channel region. The effects of metal gate electrode engineering, channel engineering (Si, Ge, GaAs, In0:53 Ga0:47 As, and InAs), and different channel thicknesses with ðAl2 O3 Þ as gate oxide having thickness of 0.8 nm on the QSCV characteristics are studied. A comparison of the QSCV characteristics is carried out for the above-mentioned channel materials, revealing a significant reduction in the inversion-mode QSCV characteristics for all the materials due to quantization that results in a decrease in the overall gate-to-channel capacitance and hence increases the threshold voltage of the MOS device. The QSCV characteristics are also useful to measure the oxide thickness, flat-band voltage, threshold voltage, maximum depletion region thickness, charge distribution in the dielectric, interface trap charge, and interface states between the channel and gate oxide before device fabrication. Key words: Double-gate MOSFET, gate-to-gate capacitance, QSCV characteristics, threshold voltage, flat-band voltage
INTRODUCTION MOS transistors are continuously scaled down to increase their performance in microelectronics industry, which also results in high-speed and high-density integrated circuits (ICs).1 This miniaturization continuously follows Moore’s law.2,3 Nevertheless, downsizing also faces serious challenges such as short-channel effects (SCEs) and direct tunneling current.4 Another problem when
(Received February 8, 2020; accepted June 30, 2020)
downsizing is the saturation of the power supply at around 0.8 V to 0.9 V,5 which limits the speed of the device. Due to these limitations, continued scaling of gate lengths to 50 nm and below will require: (i) the use of metal gate electrode engineering in nonconventional device structures such as the double-gate (DG) MOSFET, which can be scaled down to 10 nm gate lengths to meet the requirement of low off-state leakage current;6 (
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