Performance Analysis of Charge Plasma Based Five Layered Black Phosphorus-Silicon Heterostructure Tunnel Field Effect Tr
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ORIGINAL PAPER
Performance Analysis of Charge Plasma Based Five Layered Black Phosphorus-Silicon Heterostructure Tunnel Field Effect Transistor Prateek Kumar 1 & Maneesha Gupta 2 & Kunwar Singh 2 Received: 30 September 2019 / Accepted: 2 January 2020 # Springer Nature B.V. 2020
Abstract In this paper, five layered Black Phosphorus (BP) – Silicon (Si) based Tunnel Field Effect Transistor (TFET) is used to overcome the thermionic limits faced by Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and analysis of the device validates that TFET is a better alternative as nano scale transistor. To enhance the ON state current for five layered BP-Si based TFET, multi electrode (source and drain) based structure is used. For the first time, the charge plasma technique is implemented on BP. The proper work function of metal electrodes has been selected to accordingly implement the charge plasma based technique for BP and Si. Charge plasma will result in generation of electron and hole cloud depending on the work functions at source/drain electrode. Different device properties and characteristics curves viz. IDS-VGS and IDS-VDS are compared for monolayered TFET to five layered based TFET. Different analog/RF properties, as well as linear and distortion parameters of the device such as output conductance (gd), transconductance (gm), cut-off frequency (fT), third order intermodulation distortion, second and third order harmonic distortion, second and third order voltage intercept point and current intercept point, are examined for five layered BP-Si based TFET only. For five layered BP-Si based configuration, the proposed device offers a threshold voltage of 0.42 V, an average subthreshold slope of 24.14 mV/dec, ION of 1.7 × 10−4 A/μm, Drain Induced Barrier Lowering (DIBL) of 1.02 mV/V. Keywords Analog parameters . Black phosphorous . Charge plasma . Distortion . Linearity . TFET
1 Introduction With technology invading the sub-nanometer regime, length of the channel in transistors has become smaller, as an outcome short channel effects (such as DIBL, hot electron effect, impact ionization, velocity saturation, quantum tunneling through gate, etc.) in a MOSFET has been escalated [1, 2],
* Maneesha Gupta [email protected] Prateek Kumar [email protected] Kunwar Singh [email protected] 1
Faculty of Technology, University of Delhi, New Delhi 110075, India
2
Department of Electronics and Communication, Netaji Subhas University of Technology, New Delhi 110075, India
which reduces the performance of the device resulting in limitation of subthreshold slope at 60 mV/dec and lower ION/IOFF ratio [2–4]. The fundamental need for an integrated circuit in the modernized era is driven by consumption of low power and lesser area but the large size of MOSFET is a major bottleneck in achieving the above mentioned properties. A possible solution to the shortcomings associated with MOSFET is the utilization of TFET but its fabrication is generally quite complicated, as the formation of the abrupt junction and
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