Performance analysis of electrostatic plasma-based dopingless nanotube TFET
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Performance analysis of electrostatic plasma‑based dopingless nanotube TFET Ashok Kumar Gupta1 · Ashish Raman1 Received: 25 February 2020 / Accepted: 17 June 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract In this paper, the nanotube electrostatic plasma-based tunnel field-effect transistor (EP-NTTFET) has been proposed. The use of external bias on the side contacts of the source/drain region helps in the induction of charge carriers even with the use of the polysilicon electrode. The analog parameters are studied such as OFF-current, ON-current, I ON/IOFF, sub-threshold slope, threshold voltage, transconductance, TGF, cut-off frequency and DIBL with channel length (LC), Nanotube radius (TSi) and Source voltage (VS) variation. The channel length (LC) varies from 10 to 50 nm, OFF-current varies from 3.79 × 10–13 A/um to 6.79 × 10–19 A/um, sub-threshold slope improves from 36.88 mV/decade to 9.6 mV/decade and I ON/IOFF current ration improves from the order of 1 07 to 1 013. The nanotube radius ( TSi) varies from 3.5 nm to 12 nm, so ON-current varies from 2.6 × 10–5 A/um to 4.78 × 10–5 A/um, OFF-current increases and sub-threshold slope increases from 18.28 mV/decade to 26.9 mV/decade. The source voltage ( VS) varies from – 0.2 V to – 1.2 V, so ON-current varies from 7.88 × 10–6 A/um to 3 × 10–5 A/um, OFF-current increases from 6.5 × 10–19 A/um to 2.25 × 10–15 A/um, sub-threshold slope improves from 24.84 mV/decade to 20.83 mV/decade and threshold voltage decreases from 0.36 V to 0.25 V. To reduce the thermal budget with simple fabrication steps and lower random dopant fluctuations (RDFs) electrostatics plasma-based nanotube TFET is used. The proposed device EP-NTTFET provides higher ON current, higher I ON/IOFF current ratio, better sub-threshold slope, and lower threshold voltage. Keywords Nanotube · Electrostatics plasma · TFET · Short channel effects · Random dopant fluctuations (RDFs) · Nanowire · Steep-subthreshold slope
1 Introduction To facilitate multiple functional devices with minimum power consumption, the high density of low dimension devices is the most desired trend. Scaling down the device dimensions of a transistor is the main principle of the semiconductor industry. According to Moore’s law, the scaling of the device has an exponential rate [1]. To scale the device up to the submicron region or below 10 nm scale power dissipation and leakage currents are increased. Another demerit of scaling of the device is increasing the Random dopant fluctuations (RDFs) and short channel effects (SCEs) [2]. Nowadays, the low power device is treading, which has an ultra-steep subthreshold slope [3, 4]. The conventional metal * Ashok Kumar Gupta [email protected] 1
Dr BR Ambedkar National Institute of Technology, Jalandhar, India
oxide semiconductor devices (MOSFETs) exhibit the subthreshold slope 60 mV/decade, which are theoretical limits or Boltzmann limits and physics behinds it is harmonics emission of an electron [5–8] Tunnel Field Effect transistors (TFE
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