CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with paramet
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FRONTIERS IN ELECTRONIC TESTING Consulting Editor Vishwani D. Agrawal Books in the series: Nanometer Technology Designs · High Quality Delay Tests Tehranipoor, M., Ahmed, N., Vol. 38 ISBN 978-0-387-76486-3 Emerging Nanotechnologies · Test, Defect Tolerance, and Reliability Tehranipoor, M. (Ed.), Vol. 37 ISBN 978-0-387-74746-0 Oscillation-Based Test in Mixed-Signal Circuits Huertas Sánchez, G., Vázquez García de la Vega, D. (et al.) , Vol. 36 ISBN: 978-1-4020-5314-6 The Core Test Wrapper Handbook da Silva, Francisco, McLaurin, Teresa, Waayers, Tom, Vol. 35 ISBN: 0-387-30751-6 Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits Sachdev, Manoj, Pineda de Gyvez, José, Vol. 34 ISBN: 978-0-387-46546-3 Digital Timing Measurements – From Scopes and Probes to Timing and Jitter Maichen, W., Vol. 33 ISBN 0-387-32418-0 Fault-Tolerance Techniques for SRAM-based FPGAs Kastensmidt, F.L., Carro, L. (et al.), Vol. 32 ISBN 0-387-31068-1 Data Mining and Diagnosing IC Fails Huisman, L.M., Vol. 31 ISBN 0-387-24993-1 Fault Diagnosis of Analog Integrated Circuits Kabisatpathy, P., Barua, A. (et al.), Vol. 30 ISBN 0-387-25742-X Introduction to Advanced System-on-Chip Test Design and Optimi... Larsson, E., Vol. 29 ISBN: 1-4020-3207-2 Embedded Processor-Based Self-Test Gizopoulos, D. (et al.), Vol. 28 ISBN: 1-4020-2785-0 Advances in Electronic Testing Gizopoulos, D. (et al.), Vol. 27 ISBN: 0-387-29408-2 Testing Static Random Access Memories Hamdioui, S., Vol. 26 ISBN: 1-4020-7752-1 Verification by Error Modeling Radecka, K. and Zilic, Vol. 25 ISBN: 1-4020-7652-5 Elements of STIL: Principles and Applications of IEEE Std. 1450 Maston, G., Taylor, T. (et al.), Vol. 24 ISBN: 1-4020-7637-1 Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation Benso, A., Prinetto, P. (Eds.), Vol. 23 ISBN: 1-4020-7589-8 Power-Constrained Testing of VLSI Circuits Nicolici, N., Al-Hashimi, B.M., Vol. 22B ISBN: 1-4020-7235-X High Performance Memory Testing Adams, R. Dean, Vol. 22A ISBN: 1-4020-7255-4
Andrei Pavlov · Manoj Sachdev
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test
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Andrei Pavlov Intel Corporation 2501 NW 229th Street Hillsboro, OR 97124
Manoj Sachdev University of Waterloo Dept. Electrical & Computer Engineering 200 University Ave. Waterloo ON N2L 3G1 Canada
Series Editor Vishwani Agrawal Department of Electrical and Computer Engineering Auburn University Auburn, AL 36849 USA
ISBN 978-1-4020-8362-4
e-ISBN 978-1-4020-8363-1
Library of Congress Control Number: 2008924192 c 2008 Springer Science + Business Media B.V. ° No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed on acid-free paper 9
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